DRM database formats

Back to index

Filters: ARGB16161616F ×

Input formats

The percentages indicate the number of devices supporting the format and modifier. For instance, "50%" in the column for the "i915" driver would mean that half the known Intel devices support that format and modifier.

Modifier Format Planes Drivers
overlay primary amdgpu i915 xe
LINEAR ARGB16161616F 100% 100% 100% 100% 100%
I915_X_TILED ARGB16161616F 55% 41% 0% 100% 100%
I915_Y_TILED ARGB16161616F 38% 29% 0% 72% 0%
I915_4_TILED ARGB16161616F 17% 13% 0% 28% 100%
I915_4_TILED_MTL_RC_CCS ARGB16161616F 2% 2% 0% 4% 0%
I915_4_TILED_MTL_MC_CCS ARGB16161616F 2% 2% 0% 4% 0%
I915_4_TILED_MTL_RC_CCS_CC ARGB16161616F 2% 2% 0% 4% 0%
INTEL(unknown) ARGB16161616F 2% 2% 0% 0% 100%
AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_S) ARGB16161616F 32% 30% 51% 0% 0%
AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_D) ARGB16161616F 32% 32% 54% 0% 0%
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_D) ARGB16161616F 13% 10% 16% 0% 0%
AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 2, BANK_XOR_BITS = 0) ARGB16161616F 11% 10% 16% 0% 0%
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 2, PACKERS = 0) ARGB16161616F 2% 2% 3% 0% 0%
AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_D_X, PIPE_XOR_BITS = 2, BANK_XOR_BITS = 0) ARGB16161616F 11% 10% 16% 0% 0%
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2, PACKERS = 0) ARGB16161616F 2% 2% 3% 0% 0%
AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 3) ARGB16161616F 2% 2% 3% 0% 0%
AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 3) ARGB16161616F 2% 2% 3% 0% 0%
AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 4) ARGB16161616F 2% 2% 3% 0% 0%
AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4) ARGB16161616F 2% 2% 3% 0% 0%
AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_D_X, PIPE_XOR_BITS = 4, BANK_XOR_BITS = 4) ARGB16161616F 0% 2% 3% 0% 0%
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 2, PACKERS = 1) ARGB16161616F 2% 3% 5% 0% 0%
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2, PACKERS = 1) ARGB16161616F 2% 3% 5% 0% 0%
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 2, PACKERS = 2) ARGB16161616F 4% 3% 5% 0% 0%
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2, PACKERS = 2) ARGB16161616F 4% 3% 5% 0% 0%
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2) ARGB16161616F 6% 5% 8% 0% 0%
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) ARGB16161616F 6% 5% 8% 0% 0%
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 3, PACKERS = 3) ARGB16161616F 4% 3% 5% 0% 0%
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 3, PACKERS = 3) ARGB16161616F 4% 3% 5% 0% 0%
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 3) ARGB16161616F 2% 2% 3% 0% 0%
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) ARGB16161616F 2% 2% 3% 0% 0%
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 4, PACKERS = 3) ARGB16161616F 2% 2% 3% 0% 0%
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4, PACKERS = 3) ARGB16161616F 2% 2% 3% 0% 0%
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 4, PACKERS = 4) ARGB16161616F 2% 5% 8% 0% 0%
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4, PACKERS = 4) ARGB16161616F 2% 5% 8% 0% 0%
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4) ARGB16161616F 2% 2% 3% 0% 0%
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) ARGB16161616F 2% 2% 3% 0% 0%
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 5) ARGB16161616F 2% 2% 3% 0% 0%
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) ARGB16161616F 2% 2% 3% 0% 0%