LINEAR |
ARGB16161616F |
100% |
100% |
100% |
100% |

I915_X_TILED |
ARGB16161616F |
57% |
34% |
0% |
100% |

I915_Y_TILED |
ARGB16161616F |
43% |
26% |
0% |
76% |

I915_4_TILED |
ARGB16161616F |
13% |
8% |
0% |
24% |

AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_S) |
ARGB16161616F |
33% |
34% |
52% |
0% |

AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_D) |
ARGB16161616F |
33% |
36% |
55% |
0% |

AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_D) |
ARGB16161616F |
10% |
8% |
12% |
0% |

AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 2, BANK_XOR_BITS = 0) |
ARGB16161616F |
10% |
10% |
15% |
0% |

AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 2, PACKERS = 0) |
ARGB16161616F |
3% |
2% |
3% |
0% |

AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_D_X, PIPE_XOR_BITS = 2, BANK_XOR_BITS = 0) |
ARGB16161616F |
10% |
10% |
15% |
0% |

AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2, PACKERS = 0) |
ARGB16161616F |
3% |
2% |
3% |
0% |

AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 3) |
ARGB16161616F |
3% |
2% |
3% |
0% |

AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 3) |
ARGB16161616F |
3% |
2% |
3% |
0% |

AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 4) |
ARGB16161616F |
0% |
2% |
3% |
0% |

AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4) |
ARGB16161616F |
0% |
2% |
3% |
0% |

AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_D_X, PIPE_XOR_BITS = 4, BANK_XOR_BITS = 4) |
ARGB16161616F |
0% |
2% |
3% |
0% |

AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 2, PACKERS = 1) |
ARGB16161616F |
3% |
2% |
3% |
0% |

AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2, PACKERS = 1) |
ARGB16161616F |
3% |
2% |
3% |
0% |

AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 2, PACKERS = 2) |
ARGB16161616F |
3% |
4% |
6% |
0% |

AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2, PACKERS = 2) |
ARGB16161616F |
3% |
4% |
6% |
0% |

AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2) |
ARGB16161616F |
3% |
2% |
3% |
0% |

AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) |
ARGB16161616F |
3% |
2% |
3% |
0% |

AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 3, PACKERS = 3) |
ARGB16161616F |
3% |
4% |
6% |
0% |

AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 3, PACKERS = 3) |
ARGB16161616F |
3% |
4% |
6% |
0% |

AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 3) |
ARGB16161616F |
0% |
2% |
3% |
0% |

AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) |
ARGB16161616F |
0% |
2% |
3% |
0% |

AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 4, PACKERS = 3) |
ARGB16161616F |
3% |
2% |
3% |
0% |

AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4, PACKERS = 3) |
ARGB16161616F |
3% |
2% |
3% |
0% |

AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 4, PACKERS = 4) |
ARGB16161616F |
3% |
6% |
9% |
0% |

AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4, PACKERS = 4) |
ARGB16161616F |
3% |
6% |
9% |
0% |

AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4) |
ARGB16161616F |
3% |
2% |
3% |
0% |

AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) |
ARGB16161616F |
3% |
2% |
3% |
0% |

AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 5) |
ARGB16161616F |
3% |
2% |
3% |
0% |

AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) |
ARGB16161616F |
3% |
2% |
3% |
0% |