DRM database formats

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Filters: ARGB16161616F ×

Input formats

The percentages indicate the number of devices supporting the format and modifier. For instance, "50%" in the column for the "i915" driver would mean that half the known Intel devices support that format and modifier.

Modifier Format Planes Drivers
overlay primary amdgpu i915
LINEAR ARGB16161616F 100% 100% 100% 100%
I915_X_TILED ARGB16161616F 56% 31% 0% 100%
I915_Y_TILED ARGB16161616F 44% 25% 0% 80%
I915_4_TILED ARGB16161616F 11% 6% 0% 20%
AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_S) ARGB16161616F 33% 35% 52% 0%
AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_D) ARGB16161616F 33% 38% 55% 0%
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_D) ARGB16161616F 11% 8% 12% 0%
AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 2, BANK_XOR_BITS = 0) ARGB16161616F 11% 10% 15% 0%
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 2, PACKERS = 0) ARGB16161616F 4% 2% 3% 0%
AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_D_X, PIPE_XOR_BITS = 2, BANK_XOR_BITS = 0) ARGB16161616F 11% 10% 15% 0%
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2, PACKERS = 0) ARGB16161616F 4% 2% 3% 0%
AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 3) ARGB16161616F 4% 2% 3% 0%
AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 3) ARGB16161616F 4% 2% 3% 0%
AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 4) ARGB16161616F 0% 2% 3% 0%
AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4) ARGB16161616F 0% 2% 3% 0%
AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_D_X, PIPE_XOR_BITS = 4, BANK_XOR_BITS = 4) ARGB16161616F 0% 2% 3% 0%
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 2, PACKERS = 1) ARGB16161616F 4% 2% 3% 0%
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2, PACKERS = 1) ARGB16161616F 4% 2% 3% 0%
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 2, PACKERS = 2) ARGB16161616F 4% 4% 6% 0%
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2, PACKERS = 2) ARGB16161616F 4% 4% 6% 0%
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2) ARGB16161616F 4% 2% 3% 0%
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) ARGB16161616F 4% 2% 3% 0%
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 3, PACKERS = 3) ARGB16161616F 4% 4% 6% 0%
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 3, PACKERS = 3) ARGB16161616F 4% 4% 6% 0%
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 3) ARGB16161616F 0% 2% 3% 0%
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) ARGB16161616F 0% 2% 3% 0%
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 4, PACKERS = 3) ARGB16161616F 4% 2% 3% 0%
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4, PACKERS = 3) ARGB16161616F 4% 2% 3% 0%
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 4, PACKERS = 4) ARGB16161616F 0% 6% 9% 0%
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4, PACKERS = 4) ARGB16161616F 0% 6% 9% 0%
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4) ARGB16161616F 4% 2% 3% 0%
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) ARGB16161616F 4% 2% 3% 0%
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 5) ARGB16161616F 4% 2% 3% 0%
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) ARGB16161616F 4% 2% 3% 0%