| LINEAR |
ARGB16161616F |
100% |
100% |
100% |
100% |
100% |
| I915_X_TILED |
ARGB16161616F |
56% |
41% |
0% |
100% |
100% |
| I915_Y_TILED |
ARGB16161616F |
40% |
30% |
0% |
75% |
0% |
| I915_4_TILED |
ARGB16161616F |
16% |
11% |
0% |
25% |
100% |
| INTEL(unknown) |
ARGB16161616F |
2% |
2% |
0% |
0% |
100% |
| AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_S) |
ARGB16161616F |
33% |
31% |
53% |
0% |
0% |
| AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_D) |
ARGB16161616F |
33% |
33% |
56% |
0% |
0% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_D) |
ARGB16161616F |
11% |
8% |
14% |
0% |
0% |
| AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 2, BANK_XOR_BITS = 0) |
ARGB16161616F |
11% |
10% |
17% |
0% |
0% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 2, PACKERS = 0) |
ARGB16161616F |
2% |
2% |
3% |
0% |
0% |
| AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_D_X, PIPE_XOR_BITS = 2, BANK_XOR_BITS = 0) |
ARGB16161616F |
11% |
10% |
17% |
0% |
0% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2, PACKERS = 0) |
ARGB16161616F |
2% |
2% |
3% |
0% |
0% |
| AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 3) |
ARGB16161616F |
2% |
2% |
3% |
0% |
0% |
| AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 3) |
ARGB16161616F |
2% |
2% |
3% |
0% |
0% |
| AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 4) |
ARGB16161616F |
2% |
2% |
3% |
0% |
0% |
| AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4) |
ARGB16161616F |
2% |
2% |
3% |
0% |
0% |
| AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_D_X, PIPE_XOR_BITS = 4, BANK_XOR_BITS = 4) |
ARGB16161616F |
0% |
2% |
3% |
0% |
0% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 2, PACKERS = 1) |
ARGB16161616F |
2% |
3% |
6% |
0% |
0% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2, PACKERS = 1) |
ARGB16161616F |
2% |
3% |
6% |
0% |
0% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 2, PACKERS = 2) |
ARGB16161616F |
4% |
3% |
6% |
0% |
0% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2, PACKERS = 2) |
ARGB16161616F |
4% |
3% |
6% |
0% |
0% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2) |
ARGB16161616F |
4% |
3% |
6% |
0% |
0% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) |
ARGB16161616F |
4% |
3% |
6% |
0% |
0% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 3, PACKERS = 3) |
ARGB16161616F |
4% |
3% |
6% |
0% |
0% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 3, PACKERS = 3) |
ARGB16161616F |
4% |
3% |
6% |
0% |
0% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 3) |
ARGB16161616F |
2% |
2% |
3% |
0% |
0% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) |
ARGB16161616F |
2% |
2% |
3% |
0% |
0% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 4, PACKERS = 3) |
ARGB16161616F |
2% |
2% |
3% |
0% |
0% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4, PACKERS = 3) |
ARGB16161616F |
2% |
2% |
3% |
0% |
0% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 4, PACKERS = 4) |
ARGB16161616F |
2% |
5% |
8% |
0% |
0% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4, PACKERS = 4) |
ARGB16161616F |
2% |
5% |
8% |
0% |
0% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4) |
ARGB16161616F |
2% |
2% |
3% |
0% |
0% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) |
ARGB16161616F |
2% |
2% |
3% |
0% |
0% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 5) |
ARGB16161616F |
2% |
2% |
3% |
0% |
0% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) |
ARGB16161616F |
2% |
2% |
3% |
0% |
0% |