DRM database formats

Back to index

Filters: ARGB16161616F ×

Input formats

The percentages indicate the number of devices supporting the format and modifier. For instance, "50%" in the column for the "i915" driver would mean that half the known Intel devices support that format and modifier.

Modifier Format Planes Drivers
overlay primary amdgpu i915
LINEAR ARGB16161616F 100% 100% 100% 100%
I915_X_TILED ARGB16161616F 57% 37% 0% 100%
I915_Y_TILED ARGB16161616F 43% 28% 0% 75%
I915_4_TILED ARGB16161616F 14% 9% 0% 25%
AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_S) ARGB16161616F 34% 33% 53% 0%
AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_D) ARGB16161616F 34% 35% 56% 0%
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_D) ARGB16161616F 9% 7% 12% 0%
AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 2, BANK_XOR_BITS = 0) ARGB16161616F 11% 9% 15% 0%
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 2, PACKERS = 0) ARGB16161616F 3% 2% 3% 0%
AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_D_X, PIPE_XOR_BITS = 2, BANK_XOR_BITS = 0) ARGB16161616F 11% 9% 15% 0%
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2, PACKERS = 0) ARGB16161616F 3% 2% 3% 0%
AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 3) ARGB16161616F 3% 2% 3% 0%
AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 3) ARGB16161616F 3% 2% 3% 0%
AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 4) ARGB16161616F 3% 2% 3% 0%
AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4) ARGB16161616F 3% 2% 3% 0%
AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_D_X, PIPE_XOR_BITS = 4, BANK_XOR_BITS = 4) ARGB16161616F 0% 2% 3% 0%
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 2, PACKERS = 1) ARGB16161616F 3% 4% 6% 0%
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2, PACKERS = 1) ARGB16161616F 3% 4% 6% 0%
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 2, PACKERS = 2) ARGB16161616F 3% 4% 6% 0%
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2, PACKERS = 2) ARGB16161616F 3% 4% 6% 0%
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2) ARGB16161616F 3% 2% 3% 0%
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) ARGB16161616F 3% 2% 3% 0%
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 3, PACKERS = 3) ARGB16161616F 3% 4% 6% 0%
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 3, PACKERS = 3) ARGB16161616F 3% 4% 6% 0%
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 3) ARGB16161616F 0% 2% 3% 0%
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) ARGB16161616F 0% 2% 3% 0%
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 4, PACKERS = 3) ARGB16161616F 3% 2% 3% 0%
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4, PACKERS = 3) ARGB16161616F 3% 2% 3% 0%
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 4, PACKERS = 4) ARGB16161616F 3% 6% 9% 0%
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4, PACKERS = 4) ARGB16161616F 3% 6% 9% 0%
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4) ARGB16161616F 3% 2% 3% 0%
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) ARGB16161616F 3% 2% 3% 0%
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 5) ARGB16161616F 3% 2% 3% 0%
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) ARGB16161616F 3% 2% 3% 0%