DRM database formats

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Filters: ARGB16161616F ×

Input formats

The percentages indicate the number of devices supporting the format and modifier. For instance, "50%" in the column for the "i915" driver would mean that half the known Intel devices support that format and modifier.

Modifier Format Planes Drivers
overlay primary amdgpu i915 msm_drm xe
LINEAR ARGB16161616F 100% 100% 100% 100% 100% 100%
I915_X_TILED ARGB16161616F 54% 41% 0% 100% 0% 100%
I915_Y_TILED ARGB16161616F 36% 27% 0% 72% 0% 0%
I915_Y_TILED_GEN12_RC_CCS ARGB16161616F 4% 3% 0% 8% 0% 0%
I915_Y_TILED_GEN12_MC_CCS ARGB16161616F 4% 3% 0% 8% 0% 0%
I915_Y_TILED_GEN12_RC_CCS_CC ARGB16161616F 4% 3% 0% 8% 0% 0%
I915_4_TILED ARGB16161616F 18% 14% 0% 28% 0% 100%
I915_4_TILED_MTL_RC_CCS ARGB16161616F 2% 2% 0% 4% 0% 0%
I915_4_TILED_MTL_MC_CCS ARGB16161616F 2% 2% 0% 4% 0% 0%
I915_4_TILED_MTL_RC_CCS_CC ARGB16161616F 2% 2% 0% 4% 0% 0%
I915_4_TILED_LNL_CCS ARGB16161616F 2% 2% 0% 0% 0% 50%
I915_4_TILED_BMG_CCS ARGB16161616F 2% 2% 0% 0% 0% 50%
AMD(TILE_VERSION = unknown, TILE = unknown) ARGB16161616F 2% 2% 3% 0% 0% 0%
AMD(TILE_VERSION = unknown, TILE = unknown) ARGB16161616F 2% 2% 3% 0% 0% 0%
AMD(TILE_VERSION = unknown, TILE = unknown) ARGB16161616F 2% 2% 3% 0% 0% 0%
AMD(TILE_VERSION = unknown, TILE = unknown) ARGB16161616F 2% 2% 3% 0% 0% 0%
AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_S) ARGB16161616F 30% 29% 50% 0% 0% 0%
AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_D) ARGB16161616F 30% 30% 53% 0% 0% 0%
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_D) ARGB16161616F 12% 9% 16% 0% 0% 0%
AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 64B) ARGB16161616F 2% 2% 3% 0% 0% 0%
AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 64B) ARGB16161616F 2% 2% 3% 0% 0% 0%
AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 64B) ARGB16161616F 2% 2% 3% 0% 0% 0%
AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 64B) ARGB16161616F 2% 2% 3% 0% 0% 0%
AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 128B) ARGB16161616F 2% 2% 3% 0% 0% 0%
AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 128B) ARGB16161616F 2% 2% 3% 0% 0% 0%
AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 128B) ARGB16161616F 2% 2% 3% 0% 0% 0%
AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 128B) ARGB16161616F 2% 2% 3% 0% 0% 0%
AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 256B) ARGB16161616F 2% 2% 3% 0% 0% 0%
AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 256B) ARGB16161616F 2% 2% 3% 0% 0% 0%
AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 256B) ARGB16161616F 2% 2% 3% 0% 0% 0%
AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 256B) ARGB16161616F 2% 2% 3% 0% 0% 0%
AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 2, BANK_XOR_BITS = 0) ARGB16161616F 10% 9% 16% 0% 0% 0%
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 2, PACKERS = 0) ARGB16161616F 2% 2% 3% 0% 0% 0%
AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_D_X, PIPE_XOR_BITS = 2, BANK_XOR_BITS = 0) ARGB16161616F 10% 9% 16% 0% 0% 0%
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2, PACKERS = 0) ARGB16161616F 2% 2% 3% 0% 0% 0%
AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 3) ARGB16161616F 2% 2% 3% 0% 0% 0%
AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 3) ARGB16161616F 2% 2% 3% 0% 0% 0%
AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 4) ARGB16161616F 2% 2% 3% 0% 0% 0%
AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4) ARGB16161616F 2% 2% 3% 0% 0% 0%
AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_D_X, PIPE_XOR_BITS = 4, BANK_XOR_BITS = 4) ARGB16161616F 0% 2% 3% 0% 0% 0%
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 2, PACKERS = 1) ARGB16161616F 2% 3% 5% 0% 0% 0%
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2, PACKERS = 1) ARGB16161616F 2% 3% 5% 0% 0% 0%
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 2, PACKERS = 2) ARGB16161616F 4% 3% 5% 0% 0% 0%
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2, PACKERS = 2) ARGB16161616F 4% 3% 5% 0% 0% 0%
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2) ARGB16161616F 6% 5% 8% 0% 0% 0%
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) ARGB16161616F 6% 5% 8% 0% 0% 0%
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 3, PACKERS = 3) ARGB16161616F 4% 3% 5% 0% 0% 0%
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 3, PACKERS = 3) ARGB16161616F 4% 3% 5% 0% 0% 0%
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 3) ARGB16161616F 2% 2% 3% 0% 0% 0%
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) ARGB16161616F 2% 2% 3% 0% 0% 0%
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 4, PACKERS = 3) ARGB16161616F 2% 2% 3% 0% 0% 0%
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4, PACKERS = 3) ARGB16161616F 2% 2% 3% 0% 0% 0%
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 4, PACKERS = 4) ARGB16161616F 2% 5% 8% 0% 0% 0%
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4, PACKERS = 4) ARGB16161616F 2% 5% 8% 0% 0% 0%
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4) ARGB16161616F 2% 2% 3% 0% 0% 0%
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) ARGB16161616F 2% 2% 3% 0% 0% 0%
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 5) ARGB16161616F 2% 2% 3% 0% 0% 0%
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) ARGB16161616F 2% 2% 3% 0% 0% 0%