DRM database formats

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Filters: ARGB16161616F ×

Input formats

The percentages indicate the number of devices supporting the format and modifier. For instance, "50%" in the column for the "i915" driver would mean that half the known Intel devices support that format and modifier.

Modifier Format Planes Drivers
overlay primary amdgpu i915 msm_drm xe
LINEAR ARGB16161616F 100% 100% 100% 100% 100% 100%
I915_X_TILED ARGB16161616F 56% 44% 0% 100% 0% 83%
I915_Y_TILED ARGB16161616F 34% 27% 0% 71% 0% 0%
I915_Y_TILED_GEN12_RC_CCS ARGB16161616F 14% 11% 0% 29% 0% 0%
I915_Y_TILED_GEN12_MC_CCS ARGB16161616F 9% 7% 0% 19% 0% 0%
I915_Y_TILED_GEN12_RC_CCS_CC ARGB16161616F 14% 11% 0% 29% 0% 0%
I915_4_TILED ARGB16161616F 23% 18% 0% 29% 0% 100%
I915_4_TILED_DG2_RC_CCS ARGB16161616F 3% 2% 0% 6% 0% 0%
I915_4_TILED_DG2_MC_CCS ARGB16161616F 3% 2% 0% 6% 0% 0%
I915_4_TILED_DG2_RC_CCS_CC ARGB16161616F 3% 2% 0% 6% 0% 0%
I915_4_TILED_MTL_RC_CCS ARGB16161616F 6% 5% 0% 13% 0% 0%
I915_4_TILED_MTL_MC_CCS ARGB16161616F 6% 5% 0% 13% 0% 0%
I915_4_TILED_MTL_RC_CCS_CC ARGB16161616F 6% 5% 0% 13% 0% 0%
I915_4_TILED_LNL_CCS ARGB16161616F 3% 2% 0% 0% 0% 33%
I915_4_TILED_BMG_CCS ARGB16161616F 6% 5% 0% 0% 0% 67%
AMD(TILE_VERSION = unknown, TILE = unknown) ARGB16161616F 3% 2% 5% 0% 0% 0%
AMD(TILE_VERSION = unknown, TILE = unknown) ARGB16161616F 3% 2% 5% 0% 0% 0%
AMD(TILE_VERSION = unknown, TILE = unknown) ARGB16161616F 3% 2% 5% 0% 0% 0%
AMD(TILE_VERSION = unknown, TILE = unknown) ARGB16161616F 3% 2% 5% 0% 0% 0%
AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_S) ARGB16161616F 25% 24% 45% 0% 0% 0%
AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_D) ARGB16161616F 25% 26% 48% 0% 0% 0%
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_D) ARGB16161616F 12% 10% 18% 0% 0% 0%
AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 64B) ARGB16161616F 3% 2% 5% 0% 0% 0%
AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 64B) ARGB16161616F 3% 2% 5% 0% 0% 0%
AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 64B) ARGB16161616F 3% 2% 5% 0% 0% 0%
AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 64B) ARGB16161616F 3% 2% 5% 0% 0% 0%
AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 128B) ARGB16161616F 3% 2% 5% 0% 0% 0%
AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 128B) ARGB16161616F 3% 2% 5% 0% 0% 0%
AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 128B) ARGB16161616F 3% 2% 5% 0% 0% 0%
AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 128B) ARGB16161616F 3% 2% 5% 0% 0% 0%
AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 256B) ARGB16161616F 3% 2% 5% 0% 0% 0%
AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 256B) ARGB16161616F 3% 2% 5% 0% 0% 0%
AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 256B) ARGB16161616F 3% 2% 5% 0% 0% 0%
AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 256B) ARGB16161616F 3% 2% 5% 0% 0% 0%
AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 2, BANK_XOR_BITS = 0) ARGB16161616F 8% 7% 14% 0% 0% 0%
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 2, PACKERS = 0) ARGB16161616F 3% 2% 5% 0% 0% 0%
AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_D_X, PIPE_XOR_BITS = 2, BANK_XOR_BITS = 0) ARGB16161616F 8% 7% 14% 0% 0% 0%
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2, PACKERS = 0) ARGB16161616F 3% 2% 5% 0% 0% 0%
AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 3) ARGB16161616F 2% 1% 2% 0% 0% 0%
AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 3) ARGB16161616F 2% 1% 2% 0% 0% 0%
AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 4) ARGB16161616F 2% 1% 2% 0% 0% 0%
AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4) ARGB16161616F 2% 1% 2% 0% 0% 0%
AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_D_X, PIPE_XOR_BITS = 4, BANK_XOR_BITS = 4) ARGB16161616F 0% 1% 2% 0% 0% 0%
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 2, PACKERS = 1) ARGB16161616F 2% 2% 5% 0% 0% 0%
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2, PACKERS = 1) ARGB16161616F 2% 2% 5% 0% 0% 0%
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2) ARGB16161616F 3% 2% 5% 0% 0% 0%
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) ARGB16161616F 3% 2% 5% 0% 0% 0%
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 2, PACKERS = 2) ARGB16161616F 3% 2% 5% 0% 0% 0%
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2, PACKERS = 2) ARGB16161616F 3% 2% 5% 0% 0% 0%
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2) ARGB16161616F 5% 4% 7% 0% 0% 0%
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) ARGB16161616F 5% 4% 7% 0% 0% 0%
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 3, PACKERS = 3) ARGB16161616F 3% 2% 5% 0% 0% 0%
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 3, PACKERS = 3) ARGB16161616F 3% 2% 5% 0% 0% 0%
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 3) ARGB16161616F 2% 1% 2% 0% 0% 0%
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) ARGB16161616F 2% 1% 2% 0% 0% 0%
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 4, PACKERS = 3) ARGB16161616F 2% 1% 2% 0% 0% 0%
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4, PACKERS = 3) ARGB16161616F 2% 1% 2% 0% 0% 0%
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 4, PACKERS = 4) ARGB16161616F 2% 4% 7% 0% 0% 0%
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4, PACKERS = 4) ARGB16161616F 2% 4% 7% 0% 0% 0%
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4) ARGB16161616F 2% 1% 2% 0% 0% 0%
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) ARGB16161616F 2% 1% 2% 0% 0% 0%
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 5) ARGB16161616F 2% 1% 2% 0% 0% 0%
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) ARGB16161616F 2% 1% 2% 0% 0% 0%