LINEAR |
P010 |
80% |
46% |
0% |
46% |
LINEAR |
ABGR2101010 |
50% |
83% |
0% |
83% |
LINEAR |
XBGR2101010 |
50% |
83% |
0% |
83% |
LINEAR |
ARGB2101010 |
50% |
83% |
0% |
83% |
LINEAR |
XRGB2101010 |
50% |
83% |
0% |
83% |
LINEAR |
NV21 |
30% |
0% |
0% |
15% |
LINEAR |
NV12 |
80% |
49% |
0% |
49% |
LINEAR |
RGBA8888 |
100% |
83% |
0% |
83% |
LINEAR |
ABGR8888 |
100% |
83% |
0% |
83% |
LINEAR |
XBGR8888 |
100% |
83% |
0% |
83% |
LINEAR |
ARGB8888 |
100% |
100% |
100% |
100% |
LINEAR |
XRGB8888 |
100% |
100% |
0% |
100% |
LINEAR |
RGB565 |
100% |
80% |
0% |
80% |
LINEAR |
ABGR16161616 |
50% |
76% |
0% |
76% |
LINEAR |
XBGR16161616 |
50% |
76% |
0% |
76% |
LINEAR |
ARGB16161616 |
50% |
76% |
0% |
76% |
LINEAR |
XRGB16161616 |
50% |
76% |
0% |
76% |
LINEAR |
ABGR16161616F |
50% |
78% |
0% |
78% |
LINEAR |
XBGR16161616F |
50% |
78% |
0% |
78% |
LINEAR |
ARGB16161616F |
50% |
78% |
0% |
78% |
LINEAR |
XRGB16161616F |
50% |
78% |
0% |
78% |
AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_S) |
P010 |
60% |
37% |
0% |
37% |
AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_S) |
ABGR2101010 |
35% |
39% |
0% |
39% |
AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_S) |
XBGR2101010 |
35% |
39% |
0% |
39% |
AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_S) |
ARGB2101010 |
35% |
39% |
0% |
39% |
AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_S) |
XRGB2101010 |
35% |
39% |
0% |
39% |
AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_S) |
NV21 |
25% |
0% |
0% |
12% |
AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_S) |
NV12 |
60% |
39% |
0% |
39% |
AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_S) |
RGBA8888 |
80% |
39% |
0% |
39% |
AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_S) |
ABGR8888 |
80% |
39% |
0% |
39% |
AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_S) |
XBGR8888 |
80% |
39% |
0% |
39% |
AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_S) |
ARGB8888 |
80% |
39% |
0% |
39% |
AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_S) |
XRGB8888 |
80% |
39% |
0% |
39% |
AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_S) |
RGB565 |
80% |
39% |
0% |
39% |
AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_S) |
ABGR16161616 |
35% |
39% |
0% |
39% |
AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_S) |
XBGR16161616 |
35% |
39% |
0% |
39% |
AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_S) |
ARGB16161616 |
35% |
39% |
0% |
39% |
AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_S) |
XRGB16161616 |
35% |
39% |
0% |
39% |
AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_S) |
ABGR16161616F |
35% |
39% |
0% |
39% |
AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_S) |
XBGR16161616F |
35% |
39% |
0% |
39% |
AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_S) |
ARGB16161616F |
35% |
39% |
0% |
39% |
AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_S) |
XRGB16161616F |
35% |
39% |
0% |
39% |
AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_D) |
ABGR2101010 |
0% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_D) |
XBGR2101010 |
0% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_D) |
ARGB2101010 |
0% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_D) |
XRGB2101010 |
0% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_D) |
RGBA8888 |
0% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_D) |
ABGR8888 |
0% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_D) |
XBGR8888 |
0% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_D) |
ARGB8888 |
0% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_D) |
XRGB8888 |
0% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_D) |
RGB565 |
0% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_D) |
ABGR16161616 |
35% |
41% |
0% |
41% |
AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_D) |
XBGR16161616 |
35% |
41% |
0% |
41% |
AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_D) |
ARGB16161616 |
35% |
41% |
0% |
41% |
AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_D) |
XRGB16161616 |
35% |
41% |
0% |
41% |
AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_D) |
ABGR16161616F |
35% |
41% |
0% |
41% |
AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_D) |
XBGR16161616F |
35% |
41% |
0% |
41% |
AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_D) |
ARGB16161616F |
35% |
41% |
0% |
41% |
AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_D) |
XRGB16161616F |
35% |
41% |
0% |
41% |
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_D) |
ABGR16161616 |
15% |
10% |
0% |
10% |
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_D) |
XBGR16161616 |
15% |
10% |
0% |
10% |
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_D) |
ARGB16161616 |
15% |
10% |
0% |
10% |
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_D) |
XRGB16161616 |
15% |
10% |
0% |
10% |
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_D) |
ABGR16161616F |
15% |
10% |
0% |
10% |
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_D) |
XBGR16161616F |
15% |
10% |
0% |
10% |
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_D) |
ARGB16161616F |
15% |
10% |
0% |
10% |
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_D) |
XRGB16161616F |
15% |
10% |
0% |
10% |
AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 2, BANK_XOR_BITS = 0) |
P010 |
20% |
12% |
0% |
12% |
AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 2, BANK_XOR_BITS = 0) |
ABGR2101010 |
15% |
12% |
0% |
12% |
AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 2, BANK_XOR_BITS = 0) |
XBGR2101010 |
15% |
12% |
0% |
12% |
AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 2, BANK_XOR_BITS = 0) |
ARGB2101010 |
15% |
12% |
0% |
12% |
AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 2, BANK_XOR_BITS = 0) |
XRGB2101010 |
15% |
12% |
0% |
12% |
AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 2, BANK_XOR_BITS = 0) |
NV21 |
5% |
0% |
0% |
2% |
AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 2, BANK_XOR_BITS = 0) |
NV12 |
20% |
12% |
0% |
12% |
AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 2, BANK_XOR_BITS = 0) |
RGBA8888 |
25% |
12% |
0% |
12% |
AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 2, BANK_XOR_BITS = 0) |
ABGR8888 |
25% |
12% |
0% |
12% |
AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 2, BANK_XOR_BITS = 0) |
XBGR8888 |
25% |
12% |
0% |
12% |
AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 2, BANK_XOR_BITS = 0) |
ARGB8888 |
25% |
12% |
0% |
12% |
AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 2, BANK_XOR_BITS = 0) |
XRGB8888 |
25% |
12% |
0% |
12% |
AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 2, BANK_XOR_BITS = 0) |
RGB565 |
25% |
12% |
0% |
12% |
AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 2, BANK_XOR_BITS = 0) |
ABGR16161616 |
15% |
12% |
0% |
12% |
AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 2, BANK_XOR_BITS = 0) |
XBGR16161616 |
15% |
12% |
0% |
12% |
AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 2, BANK_XOR_BITS = 0) |
ARGB16161616 |
15% |
12% |
0% |
12% |
AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 2, BANK_XOR_BITS = 0) |
XRGB16161616 |
15% |
12% |
0% |
12% |
AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 2, BANK_XOR_BITS = 0) |
ABGR16161616F |
15% |
12% |
0% |
12% |
AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 2, BANK_XOR_BITS = 0) |
XBGR16161616F |
15% |
12% |
0% |
12% |
AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 2, BANK_XOR_BITS = 0) |
ARGB16161616F |
15% |
12% |
0% |
12% |
AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 2, BANK_XOR_BITS = 0) |
XRGB16161616F |
15% |
12% |
0% |
12% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 2, PACKERS = 0) |
P010 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 2, PACKERS = 0) |
ABGR2101010 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 2, PACKERS = 0) |
XBGR2101010 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 2, PACKERS = 0) |
ARGB2101010 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 2, PACKERS = 0) |
XRGB2101010 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 2, PACKERS = 0) |
NV12 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 2, PACKERS = 0) |
RGBA8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 2, PACKERS = 0) |
ABGR8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 2, PACKERS = 0) |
XBGR8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 2, PACKERS = 0) |
ARGB8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 2, PACKERS = 0) |
XRGB8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 2, PACKERS = 0) |
RGB565 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 2, PACKERS = 0) |
ABGR16161616 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 2, PACKERS = 0) |
XBGR16161616 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 2, PACKERS = 0) |
ARGB16161616 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 2, PACKERS = 0) |
XRGB16161616 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 2, PACKERS = 0) |
ABGR16161616F |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 2, PACKERS = 0) |
XBGR16161616F |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 2, PACKERS = 0) |
ARGB16161616F |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 2, PACKERS = 0) |
XRGB16161616F |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_D_X, PIPE_XOR_BITS = 2, BANK_XOR_BITS = 0) |
ABGR16161616 |
15% |
12% |
0% |
12% |
AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_D_X, PIPE_XOR_BITS = 2, BANK_XOR_BITS = 0) |
XBGR16161616 |
15% |
12% |
0% |
12% |
AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_D_X, PIPE_XOR_BITS = 2, BANK_XOR_BITS = 0) |
ARGB16161616 |
15% |
12% |
0% |
12% |
AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_D_X, PIPE_XOR_BITS = 2, BANK_XOR_BITS = 0) |
XRGB16161616 |
15% |
12% |
0% |
12% |
AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_D_X, PIPE_XOR_BITS = 2, BANK_XOR_BITS = 0) |
ABGR16161616F |
15% |
12% |
0% |
12% |
AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_D_X, PIPE_XOR_BITS = 2, BANK_XOR_BITS = 0) |
XBGR16161616F |
15% |
12% |
0% |
12% |
AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_D_X, PIPE_XOR_BITS = 2, BANK_XOR_BITS = 0) |
ARGB16161616F |
15% |
12% |
0% |
12% |
AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_D_X, PIPE_XOR_BITS = 2, BANK_XOR_BITS = 0) |
XRGB16161616F |
15% |
12% |
0% |
12% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2, PACKERS = 0) |
P010 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2, PACKERS = 0) |
ABGR2101010 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2, PACKERS = 0) |
XBGR2101010 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2, PACKERS = 0) |
ARGB2101010 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2, PACKERS = 0) |
XRGB2101010 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2, PACKERS = 0) |
NV12 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2, PACKERS = 0) |
RGBA8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2, PACKERS = 0) |
ABGR8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2, PACKERS = 0) |
XBGR8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2, PACKERS = 0) |
ARGB8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2, PACKERS = 0) |
XRGB8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2, PACKERS = 0) |
RGB565 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2, PACKERS = 0) |
ABGR16161616 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2, PACKERS = 0) |
XBGR16161616 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2, PACKERS = 0) |
ARGB16161616 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2, PACKERS = 0) |
XRGB16161616 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2, PACKERS = 0) |
ABGR16161616F |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2, PACKERS = 0) |
XBGR16161616F |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2, PACKERS = 0) |
ARGB16161616F |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2, PACKERS = 0) |
XRGB16161616F |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_S_X, DCC, DCC_INDEPENDENT_64B, DCC_MAX_COMPRESSED_BLOCK = 64B, PIPE_XOR_BITS = 2, BANK_XOR_BITS = 0, RB = 0) |
ABGR2101010 |
15% |
12% |
0% |
12% |
AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_S_X, DCC, DCC_INDEPENDENT_64B, DCC_MAX_COMPRESSED_BLOCK = 64B, PIPE_XOR_BITS = 2, BANK_XOR_BITS = 0, RB = 0) |
XBGR2101010 |
15% |
12% |
0% |
12% |
AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_S_X, DCC, DCC_INDEPENDENT_64B, DCC_MAX_COMPRESSED_BLOCK = 64B, PIPE_XOR_BITS = 2, BANK_XOR_BITS = 0, RB = 0) |
ARGB2101010 |
15% |
12% |
0% |
12% |
AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_S_X, DCC, DCC_INDEPENDENT_64B, DCC_MAX_COMPRESSED_BLOCK = 64B, PIPE_XOR_BITS = 2, BANK_XOR_BITS = 0, RB = 0) |
XRGB2101010 |
15% |
12% |
0% |
12% |
AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_S_X, DCC, DCC_INDEPENDENT_64B, DCC_MAX_COMPRESSED_BLOCK = 64B, PIPE_XOR_BITS = 2, BANK_XOR_BITS = 0, RB = 0) |
RGBA8888 |
25% |
12% |
0% |
12% |
AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_S_X, DCC, DCC_INDEPENDENT_64B, DCC_MAX_COMPRESSED_BLOCK = 64B, PIPE_XOR_BITS = 2, BANK_XOR_BITS = 0, RB = 0) |
ABGR8888 |
25% |
12% |
0% |
12% |
AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_S_X, DCC, DCC_INDEPENDENT_64B, DCC_MAX_COMPRESSED_BLOCK = 64B, PIPE_XOR_BITS = 2, BANK_XOR_BITS = 0, RB = 0) |
XBGR8888 |
25% |
12% |
0% |
12% |
AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_S_X, DCC, DCC_INDEPENDENT_64B, DCC_MAX_COMPRESSED_BLOCK = 64B, PIPE_XOR_BITS = 2, BANK_XOR_BITS = 0, RB = 0) |
ARGB8888 |
25% |
12% |
0% |
12% |
AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_S_X, DCC, DCC_INDEPENDENT_64B, DCC_MAX_COMPRESSED_BLOCK = 64B, PIPE_XOR_BITS = 2, BANK_XOR_BITS = 0, RB = 0) |
XRGB8888 |
25% |
12% |
0% |
12% |
AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_S_X, DCC, DCC_INDEPENDENT_64B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, BANK_XOR_BITS = 0, RB = 0) |
ABGR2101010 |
10% |
7% |
0% |
7% |
AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_S_X, DCC, DCC_INDEPENDENT_64B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, BANK_XOR_BITS = 0, RB = 0) |
XBGR2101010 |
10% |
7% |
0% |
7% |
AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_S_X, DCC, DCC_INDEPENDENT_64B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, BANK_XOR_BITS = 0, RB = 0) |
ARGB2101010 |
10% |
7% |
0% |
7% |
AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_S_X, DCC, DCC_INDEPENDENT_64B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, BANK_XOR_BITS = 0, RB = 0) |
XRGB2101010 |
10% |
7% |
0% |
7% |
AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_S_X, DCC, DCC_INDEPENDENT_64B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, BANK_XOR_BITS = 0, RB = 0) |
RGBA8888 |
15% |
7% |
0% |
7% |
AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_S_X, DCC, DCC_INDEPENDENT_64B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, BANK_XOR_BITS = 0, RB = 0) |
ABGR8888 |
15% |
7% |
0% |
7% |
AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_S_X, DCC, DCC_INDEPENDENT_64B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, BANK_XOR_BITS = 0, RB = 0) |
XBGR8888 |
15% |
7% |
0% |
7% |
AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_S_X, DCC, DCC_INDEPENDENT_64B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, BANK_XOR_BITS = 0, RB = 0) |
ARGB8888 |
15% |
7% |
0% |
7% |
AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_S_X, DCC, DCC_INDEPENDENT_64B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, BANK_XOR_BITS = 0, RB = 0) |
XRGB8888 |
15% |
7% |
0% |
7% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, PACKERS = 0) |
ABGR2101010 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, PACKERS = 0) |
XBGR2101010 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, PACKERS = 0) |
ARGB2101010 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, PACKERS = 0) |
XRGB2101010 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, PACKERS = 0) |
RGBA8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, PACKERS = 0) |
ABGR8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, PACKERS = 0) |
XBGR8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, PACKERS = 0) |
ARGB8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, PACKERS = 0) |
XRGB8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, PACKERS = 0) |
ABGR2101010 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, PACKERS = 0) |
XBGR2101010 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, PACKERS = 0) |
ARGB2101010 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, PACKERS = 0) |
XRGB2101010 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, PACKERS = 0) |
RGBA8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, PACKERS = 0) |
ABGR8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, PACKERS = 0) |
XBGR8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, PACKERS = 0) |
ARGB8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, PACKERS = 0) |
XRGB8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, PACKERS = 0) |
ABGR2101010 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, PACKERS = 0) |
XBGR2101010 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, PACKERS = 0) |
ARGB2101010 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, PACKERS = 0) |
XRGB2101010 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, PACKERS = 0) |
RGBA8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, PACKERS = 0) |
ABGR8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, PACKERS = 0) |
XBGR8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, PACKERS = 0) |
ARGB8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, PACKERS = 0) |
XRGB8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, PACKERS = 0) |
ABGR2101010 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, PACKERS = 0) |
XBGR2101010 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, PACKERS = 0) |
ARGB2101010 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, PACKERS = 0) |
XRGB2101010 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, PACKERS = 0) |
RGBA8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, PACKERS = 0) |
ABGR8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, PACKERS = 0) |
XBGR8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, PACKERS = 0) |
ARGB8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, PACKERS = 0) |
XRGB8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 3) |
P010 |
0% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 3) |
ABGR2101010 |
0% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 3) |
XBGR2101010 |
0% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 3) |
ARGB2101010 |
0% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 3) |
XRGB2101010 |
0% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 3) |
NV12 |
0% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 3) |
RGBA8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 3) |
ABGR8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 3) |
XBGR8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 3) |
ARGB8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 3) |
XRGB8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 3) |
RGB565 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 3) |
ABGR16161616 |
0% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 3) |
XBGR16161616 |
0% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 3) |
ARGB16161616 |
0% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 3) |
XRGB16161616 |
0% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 3) |
ABGR16161616F |
0% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 3) |
XBGR16161616F |
0% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 3) |
ARGB16161616F |
0% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 3) |
XRGB16161616F |
0% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 3) |
P010 |
0% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 3) |
ABGR2101010 |
0% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 3) |
XBGR2101010 |
0% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 3) |
ARGB2101010 |
0% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 3) |
XRGB2101010 |
0% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 3) |
NV12 |
0% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 3) |
RGBA8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 3) |
ABGR8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 3) |
XBGR8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 3) |
ARGB8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 3) |
XRGB8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 3) |
RGB565 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 3) |
ABGR16161616 |
0% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 3) |
XBGR16161616 |
0% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 3) |
ARGB16161616 |
0% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 3) |
XRGB16161616 |
0% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 3) |
ABGR16161616F |
0% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 3) |
XBGR16161616F |
0% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 3) |
ARGB16161616F |
0% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 3) |
XRGB16161616F |
0% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 3) |
ABGR2101010 |
0% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 3) |
XBGR2101010 |
0% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 3) |
ARGB2101010 |
0% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 3) |
XRGB2101010 |
0% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 3) |
RGBA8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 3) |
ABGR8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 3) |
XBGR8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 3) |
ARGB8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 3) |
XRGB8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 3) |
ABGR2101010 |
0% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 3) |
XBGR2101010 |
0% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 3) |
ARGB2101010 |
0% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 3) |
XRGB2101010 |
0% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 3) |
RGBA8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 3) |
ABGR8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 3) |
XBGR8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 3) |
ARGB8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 3) |
XRGB8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 4) |
P010 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 4) |
ABGR2101010 |
0% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 4) |
XBGR2101010 |
0% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 4) |
ARGB2101010 |
0% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 4) |
XRGB2101010 |
0% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 4) |
NV21 |
5% |
0% |
0% |
2% |
AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 4) |
NV12 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 4) |
RGBA8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 4) |
ABGR8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 4) |
XBGR8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 4) |
ARGB8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 4) |
XRGB8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 4) |
RGB565 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 4) |
ABGR16161616 |
0% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 4) |
XBGR16161616 |
0% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 4) |
ARGB16161616 |
0% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 4) |
XRGB16161616 |
0% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 4) |
ABGR16161616F |
0% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 4) |
XBGR16161616F |
0% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 4) |
ARGB16161616F |
0% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 4) |
XRGB16161616F |
0% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4) |
P010 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4) |
ABGR2101010 |
0% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4) |
XBGR2101010 |
0% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4) |
ARGB2101010 |
0% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4) |
XRGB2101010 |
0% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4) |
NV21 |
5% |
0% |
0% |
2% |
AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4) |
NV12 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4) |
RGBA8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4) |
ABGR8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4) |
XBGR8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4) |
ARGB8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4) |
XRGB8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4) |
RGB565 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4) |
ABGR16161616 |
0% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4) |
XBGR16161616 |
0% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4) |
ARGB16161616 |
0% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4) |
XRGB16161616 |
0% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4) |
ABGR16161616F |
0% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4) |
XBGR16161616F |
0% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4) |
ARGB16161616F |
0% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4) |
XRGB16161616F |
0% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 4) |
ABGR2101010 |
0% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 4) |
XBGR2101010 |
0% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 4) |
ARGB2101010 |
0% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 4) |
XRGB2101010 |
0% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 4) |
RGBA8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 4) |
ABGR8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 4) |
XBGR8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 4) |
ARGB8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 4) |
XRGB8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 4) |
ABGR2101010 |
0% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 4) |
XBGR2101010 |
0% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 4) |
ARGB2101010 |
0% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 4) |
XRGB2101010 |
0% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 4) |
RGBA8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 4) |
ABGR8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 4) |
XBGR8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 4) |
ARGB8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 4) |
XRGB8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_D_X, PIPE_XOR_BITS = 4, BANK_XOR_BITS = 4) |
ABGR2101010 |
0% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_D_X, PIPE_XOR_BITS = 4, BANK_XOR_BITS = 4) |
XBGR2101010 |
0% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_D_X, PIPE_XOR_BITS = 4, BANK_XOR_BITS = 4) |
ARGB2101010 |
0% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_D_X, PIPE_XOR_BITS = 4, BANK_XOR_BITS = 4) |
XRGB2101010 |
0% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_D_X, PIPE_XOR_BITS = 4, BANK_XOR_BITS = 4) |
RGBA8888 |
0% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_D_X, PIPE_XOR_BITS = 4, BANK_XOR_BITS = 4) |
ABGR8888 |
0% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_D_X, PIPE_XOR_BITS = 4, BANK_XOR_BITS = 4) |
XBGR8888 |
0% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_D_X, PIPE_XOR_BITS = 4, BANK_XOR_BITS = 4) |
ARGB8888 |
0% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_D_X, PIPE_XOR_BITS = 4, BANK_XOR_BITS = 4) |
XRGB8888 |
0% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_D_X, PIPE_XOR_BITS = 4, BANK_XOR_BITS = 4) |
RGB565 |
0% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_D_X, PIPE_XOR_BITS = 4, BANK_XOR_BITS = 4) |
ABGR16161616 |
0% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_D_X, PIPE_XOR_BITS = 4, BANK_XOR_BITS = 4) |
XBGR16161616 |
0% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_D_X, PIPE_XOR_BITS = 4, BANK_XOR_BITS = 4) |
ARGB16161616 |
0% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_D_X, PIPE_XOR_BITS = 4, BANK_XOR_BITS = 4) |
XRGB16161616 |
0% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_D_X, PIPE_XOR_BITS = 4, BANK_XOR_BITS = 4) |
ABGR16161616F |
0% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_D_X, PIPE_XOR_BITS = 4, BANK_XOR_BITS = 4) |
XBGR16161616F |
0% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_D_X, PIPE_XOR_BITS = 4, BANK_XOR_BITS = 4) |
ARGB16161616F |
0% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_D_X, PIPE_XOR_BITS = 4, BANK_XOR_BITS = 4) |
XRGB16161616F |
0% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 2, PACKERS = 2) |
P010 |
10% |
5% |
0% |
5% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 2, PACKERS = 2) |
ABGR2101010 |
5% |
5% |
0% |
5% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 2, PACKERS = 2) |
XBGR2101010 |
5% |
5% |
0% |
5% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 2, PACKERS = 2) |
ARGB2101010 |
5% |
5% |
0% |
5% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 2, PACKERS = 2) |
XRGB2101010 |
5% |
5% |
0% |
5% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 2, PACKERS = 2) |
NV21 |
5% |
0% |
0% |
2% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 2, PACKERS = 2) |
NV12 |
10% |
5% |
0% |
5% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 2, PACKERS = 2) |
RGBA8888 |
10% |
5% |
0% |
5% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 2, PACKERS = 2) |
ABGR8888 |
10% |
5% |
0% |
5% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 2, PACKERS = 2) |
XBGR8888 |
10% |
5% |
0% |
5% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 2, PACKERS = 2) |
ARGB8888 |
10% |
5% |
0% |
5% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 2, PACKERS = 2) |
XRGB8888 |
10% |
5% |
0% |
5% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 2, PACKERS = 2) |
RGB565 |
10% |
5% |
0% |
5% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 2, PACKERS = 2) |
ABGR16161616 |
5% |
5% |
0% |
5% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 2, PACKERS = 2) |
XBGR16161616 |
5% |
5% |
0% |
5% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 2, PACKERS = 2) |
ARGB16161616 |
5% |
5% |
0% |
5% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 2, PACKERS = 2) |
XRGB16161616 |
5% |
5% |
0% |
5% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 2, PACKERS = 2) |
ABGR16161616F |
5% |
5% |
0% |
5% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 2, PACKERS = 2) |
XBGR16161616F |
5% |
5% |
0% |
5% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 2, PACKERS = 2) |
ARGB16161616F |
5% |
5% |
0% |
5% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 2, PACKERS = 2) |
XRGB16161616F |
5% |
5% |
0% |
5% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2, PACKERS = 2) |
P010 |
10% |
5% |
0% |
5% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2, PACKERS = 2) |
ABGR2101010 |
5% |
5% |
0% |
5% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2, PACKERS = 2) |
XBGR2101010 |
5% |
5% |
0% |
5% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2, PACKERS = 2) |
ARGB2101010 |
5% |
5% |
0% |
5% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2, PACKERS = 2) |
XRGB2101010 |
5% |
5% |
0% |
5% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2, PACKERS = 2) |
NV21 |
5% |
0% |
0% |
2% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2, PACKERS = 2) |
NV12 |
10% |
5% |
0% |
5% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2, PACKERS = 2) |
RGBA8888 |
10% |
5% |
0% |
5% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2, PACKERS = 2) |
ABGR8888 |
10% |
5% |
0% |
5% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2, PACKERS = 2) |
XBGR8888 |
10% |
5% |
0% |
5% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2, PACKERS = 2) |
ARGB8888 |
10% |
5% |
0% |
5% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2, PACKERS = 2) |
XRGB8888 |
10% |
5% |
0% |
5% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2, PACKERS = 2) |
RGB565 |
10% |
5% |
0% |
5% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2, PACKERS = 2) |
ABGR16161616 |
5% |
5% |
0% |
5% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2, PACKERS = 2) |
XBGR16161616 |
5% |
5% |
0% |
5% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2, PACKERS = 2) |
ARGB16161616 |
5% |
5% |
0% |
5% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2, PACKERS = 2) |
XRGB16161616 |
5% |
5% |
0% |
5% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2, PACKERS = 2) |
ABGR16161616F |
5% |
5% |
0% |
5% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2, PACKERS = 2) |
XBGR16161616F |
5% |
5% |
0% |
5% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2, PACKERS = 2) |
ARGB16161616F |
5% |
5% |
0% |
5% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2, PACKERS = 2) |
XRGB16161616F |
5% |
5% |
0% |
5% |
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2) |
P010 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2) |
ABGR2101010 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2) |
XBGR2101010 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2) |
ARGB2101010 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2) |
XRGB2101010 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2) |
NV12 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2) |
RGBA8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2) |
ABGR8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2) |
XBGR8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2) |
ARGB8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2) |
XRGB8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2) |
RGB565 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2) |
ABGR16161616 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2) |
XBGR16161616 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2) |
ARGB16161616 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2) |
XRGB16161616 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2) |
ABGR16161616F |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2) |
XBGR16161616F |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2) |
ARGB16161616F |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2) |
XRGB16161616F |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) |
P010 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) |
ABGR2101010 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) |
XBGR2101010 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) |
ARGB2101010 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) |
XRGB2101010 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) |
NV12 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) |
RGBA8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) |
ABGR8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) |
XBGR8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) |
ARGB8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) |
XRGB8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) |
RGB565 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) |
ABGR16161616 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) |
XBGR16161616 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) |
ARGB16161616 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) |
XRGB16161616 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) |
ABGR16161616F |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) |
XBGR16161616F |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) |
ARGB16161616F |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) |
XRGB16161616F |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, PIPE_XOR_BITS = 2) |
ABGR2101010 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, PIPE_XOR_BITS = 2) |
XBGR2101010 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, PIPE_XOR_BITS = 2) |
ARGB2101010 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, PIPE_XOR_BITS = 2) |
XRGB2101010 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, PIPE_XOR_BITS = 2) |
RGBA8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, PIPE_XOR_BITS = 2) |
ABGR8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, PIPE_XOR_BITS = 2) |
XBGR8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, PIPE_XOR_BITS = 2) |
ARGB8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, PIPE_XOR_BITS = 2) |
XRGB8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B) |
ABGR2101010 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B) |
XBGR2101010 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B) |
ARGB2101010 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B) |
XRGB2101010 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B) |
RGBA8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B) |
ABGR8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B) |
XBGR8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B) |
ARGB8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B) |
XRGB8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, PIPE_XOR_BITS = 2) |
ABGR2101010 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, PIPE_XOR_BITS = 2) |
XBGR2101010 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, PIPE_XOR_BITS = 2) |
ARGB2101010 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, PIPE_XOR_BITS = 2) |
XRGB2101010 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, PIPE_XOR_BITS = 2) |
RGBA8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, PIPE_XOR_BITS = 2) |
ABGR8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, PIPE_XOR_BITS = 2) |
XBGR8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, PIPE_XOR_BITS = 2) |
ARGB8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, PIPE_XOR_BITS = 2) |
XRGB8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B) |
ABGR2101010 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B) |
XBGR2101010 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B) |
ARGB2101010 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B) |
XRGB2101010 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B) |
RGBA8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B) |
ABGR8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B) |
XBGR8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B) |
ARGB8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B) |
XRGB8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, PIPE_XOR_BITS = 2) |
ABGR2101010 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, PIPE_XOR_BITS = 2) |
XBGR2101010 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, PIPE_XOR_BITS = 2) |
ARGB2101010 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, PIPE_XOR_BITS = 2) |
XRGB2101010 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, PIPE_XOR_BITS = 2) |
RGBA8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, PIPE_XOR_BITS = 2) |
ABGR8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, PIPE_XOR_BITS = 2) |
XBGR8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, PIPE_XOR_BITS = 2) |
ARGB8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, PIPE_XOR_BITS = 2) |
XRGB8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B) |
ABGR2101010 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B) |
XBGR2101010 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B) |
ARGB2101010 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B) |
XRGB2101010 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B) |
RGBA8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B) |
ABGR8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B) |
XBGR8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B) |
ARGB8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B) |
XRGB8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, PIPE_XOR_BITS = 2) |
ABGR2101010 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, PIPE_XOR_BITS = 2) |
XBGR2101010 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, PIPE_XOR_BITS = 2) |
ARGB2101010 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, PIPE_XOR_BITS = 2) |
XRGB2101010 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, PIPE_XOR_BITS = 2) |
RGBA8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, PIPE_XOR_BITS = 2) |
ABGR8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, PIPE_XOR_BITS = 2) |
XBGR8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, PIPE_XOR_BITS = 2) |
ARGB8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, PIPE_XOR_BITS = 2) |
XRGB8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B) |
ABGR2101010 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B) |
XBGR2101010 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B) |
ARGB2101010 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B) |
XRGB2101010 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B) |
RGBA8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B) |
ABGR8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B) |
XBGR8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B) |
ARGB8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B) |
XRGB8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, PACKERS = 2) |
ABGR2101010 |
5% |
5% |
0% |
5% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, PACKERS = 2) |
XBGR2101010 |
5% |
5% |
0% |
5% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, PACKERS = 2) |
ARGB2101010 |
5% |
5% |
0% |
5% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, PACKERS = 2) |
XRGB2101010 |
5% |
5% |
0% |
5% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, PACKERS = 2) |
RGBA8888 |
10% |
5% |
0% |
5% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, PACKERS = 2) |
ABGR8888 |
10% |
5% |
0% |
5% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, PACKERS = 2) |
XBGR8888 |
10% |
5% |
0% |
5% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, PACKERS = 2) |
ARGB8888 |
10% |
5% |
0% |
5% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, PACKERS = 2) |
XRGB8888 |
10% |
5% |
0% |
5% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, PACKERS = 2) |
ABGR2101010 |
5% |
5% |
0% |
5% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, PACKERS = 2) |
XBGR2101010 |
5% |
5% |
0% |
5% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, PACKERS = 2) |
ARGB2101010 |
5% |
5% |
0% |
5% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, PACKERS = 2) |
XRGB2101010 |
5% |
5% |
0% |
5% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, PACKERS = 2) |
RGBA8888 |
10% |
5% |
0% |
5% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, PACKERS = 2) |
ABGR8888 |
10% |
5% |
0% |
5% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, PACKERS = 2) |
XBGR8888 |
10% |
5% |
0% |
5% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, PACKERS = 2) |
ARGB8888 |
10% |
5% |
0% |
5% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, PACKERS = 2) |
XRGB8888 |
10% |
5% |
0% |
5% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, PACKERS = 2) |
ABGR2101010 |
5% |
5% |
0% |
5% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, PACKERS = 2) |
XBGR2101010 |
5% |
5% |
0% |
5% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, PACKERS = 2) |
ARGB2101010 |
5% |
5% |
0% |
5% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, PACKERS = 2) |
XRGB2101010 |
5% |
5% |
0% |
5% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, PACKERS = 2) |
RGBA8888 |
10% |
5% |
0% |
5% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, PACKERS = 2) |
ABGR8888 |
10% |
5% |
0% |
5% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, PACKERS = 2) |
XBGR8888 |
10% |
5% |
0% |
5% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, PACKERS = 2) |
ARGB8888 |
10% |
5% |
0% |
5% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, PACKERS = 2) |
XRGB8888 |
10% |
5% |
0% |
5% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, PACKERS = 2) |
ABGR2101010 |
5% |
5% |
0% |
5% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, PACKERS = 2) |
XBGR2101010 |
5% |
5% |
0% |
5% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, PACKERS = 2) |
ARGB2101010 |
5% |
5% |
0% |
5% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, PACKERS = 2) |
XRGB2101010 |
5% |
5% |
0% |
5% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, PACKERS = 2) |
RGBA8888 |
10% |
5% |
0% |
5% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, PACKERS = 2) |
ABGR8888 |
10% |
5% |
0% |
5% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, PACKERS = 2) |
XBGR8888 |
10% |
5% |
0% |
5% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, PACKERS = 2) |
ARGB8888 |
10% |
5% |
0% |
5% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, PACKERS = 2) |
XRGB8888 |
10% |
5% |
0% |
5% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 3, PACKERS = 3) |
P010 |
5% |
5% |
0% |
5% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 3, PACKERS = 3) |
ABGR2101010 |
5% |
5% |
0% |
5% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 3, PACKERS = 3) |
XBGR2101010 |
5% |
5% |
0% |
5% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 3, PACKERS = 3) |
ARGB2101010 |
5% |
5% |
0% |
5% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 3, PACKERS = 3) |
XRGB2101010 |
5% |
5% |
0% |
5% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 3, PACKERS = 3) |
NV12 |
5% |
5% |
0% |
5% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 3, PACKERS = 3) |
RGBA8888 |
10% |
5% |
0% |
5% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 3, PACKERS = 3) |
ABGR8888 |
10% |
5% |
0% |
5% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 3, PACKERS = 3) |
XBGR8888 |
10% |
5% |
0% |
5% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 3, PACKERS = 3) |
ARGB8888 |
10% |
5% |
0% |
5% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 3, PACKERS = 3) |
XRGB8888 |
10% |
5% |
0% |
5% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 3, PACKERS = 3) |
RGB565 |
10% |
5% |
0% |
5% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 3, PACKERS = 3) |
ABGR16161616 |
5% |
5% |
0% |
5% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 3, PACKERS = 3) |
XBGR16161616 |
5% |
5% |
0% |
5% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 3, PACKERS = 3) |
ARGB16161616 |
5% |
5% |
0% |
5% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 3, PACKERS = 3) |
XRGB16161616 |
5% |
5% |
0% |
5% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 3, PACKERS = 3) |
ABGR16161616F |
5% |
5% |
0% |
5% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 3, PACKERS = 3) |
XBGR16161616F |
5% |
5% |
0% |
5% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 3, PACKERS = 3) |
ARGB16161616F |
5% |
5% |
0% |
5% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 3, PACKERS = 3) |
XRGB16161616F |
5% |
5% |
0% |
5% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 3, PACKERS = 3) |
P010 |
5% |
5% |
0% |
5% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 3, PACKERS = 3) |
ABGR2101010 |
5% |
5% |
0% |
5% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 3, PACKERS = 3) |
XBGR2101010 |
5% |
5% |
0% |
5% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 3, PACKERS = 3) |
ARGB2101010 |
5% |
5% |
0% |
5% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 3, PACKERS = 3) |
XRGB2101010 |
5% |
5% |
0% |
5% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 3, PACKERS = 3) |
NV12 |
5% |
5% |
0% |
5% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 3, PACKERS = 3) |
RGBA8888 |
10% |
5% |
0% |
5% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 3, PACKERS = 3) |
ABGR8888 |
10% |
5% |
0% |
5% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 3, PACKERS = 3) |
XBGR8888 |
10% |
5% |
0% |
5% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 3, PACKERS = 3) |
ARGB8888 |
10% |
5% |
0% |
5% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 3, PACKERS = 3) |
XRGB8888 |
10% |
5% |
0% |
5% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 3, PACKERS = 3) |
RGB565 |
10% |
5% |
0% |
5% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 3, PACKERS = 3) |
ABGR16161616 |
5% |
5% |
0% |
5% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 3, PACKERS = 3) |
XBGR16161616 |
5% |
5% |
0% |
5% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 3, PACKERS = 3) |
ARGB16161616 |
5% |
5% |
0% |
5% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 3, PACKERS = 3) |
XRGB16161616 |
5% |
5% |
0% |
5% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 3, PACKERS = 3) |
ABGR16161616F |
5% |
5% |
0% |
5% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 3, PACKERS = 3) |
XBGR16161616F |
5% |
5% |
0% |
5% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 3, PACKERS = 3) |
ARGB16161616F |
5% |
5% |
0% |
5% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 3, PACKERS = 3) |
XRGB16161616F |
5% |
5% |
0% |
5% |
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 3) |
P010 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 3) |
ABGR2101010 |
0% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 3) |
XBGR2101010 |
0% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 3) |
ARGB2101010 |
0% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 3) |
XRGB2101010 |
0% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 3) |
NV21 |
5% |
0% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 3) |
NV12 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 3) |
RGBA8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 3) |
ABGR8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 3) |
XBGR8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 3) |
ARGB8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 3) |
XRGB8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 3) |
RGB565 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 3) |
ABGR16161616 |
0% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 3) |
XBGR16161616 |
0% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 3) |
ARGB16161616 |
0% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 3) |
XRGB16161616 |
0% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 3) |
ABGR16161616F |
0% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 3) |
XBGR16161616F |
0% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 3) |
ARGB16161616F |
0% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 3) |
XRGB16161616F |
0% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) |
P010 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) |
ABGR2101010 |
0% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) |
XBGR2101010 |
0% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) |
ARGB2101010 |
0% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) |
XRGB2101010 |
0% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) |
NV21 |
5% |
0% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) |
NV12 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) |
RGBA8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) |
ABGR8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) |
XBGR8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) |
ARGB8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) |
XRGB8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) |
RGB565 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) |
ABGR16161616 |
0% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) |
XBGR16161616 |
0% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) |
ARGB16161616 |
0% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) |
XRGB16161616 |
0% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) |
ABGR16161616F |
0% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) |
XBGR16161616F |
0% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) |
ARGB16161616F |
0% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) |
XRGB16161616F |
0% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, PIPE_XOR_BITS = 3) |
ABGR2101010 |
0% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, PIPE_XOR_BITS = 3) |
XBGR2101010 |
0% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, PIPE_XOR_BITS = 3) |
ARGB2101010 |
0% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, PIPE_XOR_BITS = 3) |
XRGB2101010 |
0% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, PIPE_XOR_BITS = 3) |
RGBA8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, PIPE_XOR_BITS = 3) |
ABGR8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, PIPE_XOR_BITS = 3) |
XBGR8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, PIPE_XOR_BITS = 3) |
ARGB8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, PIPE_XOR_BITS = 3) |
XRGB8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B) |
ABGR2101010 |
0% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B) |
XBGR2101010 |
0% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B) |
ARGB2101010 |
0% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B) |
XRGB2101010 |
0% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B) |
RGBA8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B) |
ABGR8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B) |
XBGR8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B) |
ARGB8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B) |
XRGB8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, PIPE_XOR_BITS = 3) |
ABGR2101010 |
0% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, PIPE_XOR_BITS = 3) |
XBGR2101010 |
0% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, PIPE_XOR_BITS = 3) |
ARGB2101010 |
0% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, PIPE_XOR_BITS = 3) |
XRGB2101010 |
0% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, PIPE_XOR_BITS = 3) |
RGBA8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, PIPE_XOR_BITS = 3) |
ABGR8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, PIPE_XOR_BITS = 3) |
XBGR8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, PIPE_XOR_BITS = 3) |
ARGB8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, PIPE_XOR_BITS = 3) |
XRGB8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B) |
ABGR2101010 |
0% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B) |
XBGR2101010 |
0% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B) |
ARGB2101010 |
0% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B) |
XRGB2101010 |
0% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B) |
RGBA8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B) |
ABGR8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B) |
XBGR8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B) |
ARGB8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B) |
XRGB8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, PIPE_XOR_BITS = 3) |
ABGR2101010 |
0% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, PIPE_XOR_BITS = 3) |
XBGR2101010 |
0% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, PIPE_XOR_BITS = 3) |
ARGB2101010 |
0% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, PIPE_XOR_BITS = 3) |
XRGB2101010 |
0% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, PIPE_XOR_BITS = 3) |
RGBA8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, PIPE_XOR_BITS = 3) |
ABGR8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, PIPE_XOR_BITS = 3) |
XBGR8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, PIPE_XOR_BITS = 3) |
ARGB8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, PIPE_XOR_BITS = 3) |
XRGB8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B) |
ABGR2101010 |
0% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B) |
XBGR2101010 |
0% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B) |
ARGB2101010 |
0% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B) |
XRGB2101010 |
0% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B) |
RGBA8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B) |
ABGR8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B) |
XBGR8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B) |
ARGB8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B) |
XRGB8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, PIPE_XOR_BITS = 3) |
ABGR2101010 |
0% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, PIPE_XOR_BITS = 3) |
XBGR2101010 |
0% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, PIPE_XOR_BITS = 3) |
ARGB2101010 |
0% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, PIPE_XOR_BITS = 3) |
XRGB2101010 |
0% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, PIPE_XOR_BITS = 3) |
RGBA8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, PIPE_XOR_BITS = 3) |
ABGR8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, PIPE_XOR_BITS = 3) |
XBGR8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, PIPE_XOR_BITS = 3) |
ARGB8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, PIPE_XOR_BITS = 3) |
XRGB8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B) |
ABGR2101010 |
0% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B) |
XBGR2101010 |
0% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B) |
ARGB2101010 |
0% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B) |
XRGB2101010 |
0% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B) |
RGBA8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B) |
ABGR8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B) |
XBGR8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B) |
ARGB8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B) |
XRGB8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 3, PACKERS = 3) |
ABGR2101010 |
5% |
5% |
0% |
5% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 3, PACKERS = 3) |
XBGR2101010 |
5% |
5% |
0% |
5% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 3, PACKERS = 3) |
ARGB2101010 |
5% |
5% |
0% |
5% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 3, PACKERS = 3) |
XRGB2101010 |
5% |
5% |
0% |
5% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 3, PACKERS = 3) |
RGBA8888 |
10% |
5% |
0% |
5% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 3, PACKERS = 3) |
ABGR8888 |
10% |
5% |
0% |
5% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 3, PACKERS = 3) |
XBGR8888 |
10% |
5% |
0% |
5% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 3, PACKERS = 3) |
ARGB8888 |
10% |
5% |
0% |
5% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 3, PACKERS = 3) |
XRGB8888 |
10% |
5% |
0% |
5% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 3, PACKERS = 3) |
ABGR2101010 |
5% |
5% |
0% |
5% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 3, PACKERS = 3) |
XBGR2101010 |
5% |
5% |
0% |
5% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 3, PACKERS = 3) |
ARGB2101010 |
5% |
5% |
0% |
5% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 3, PACKERS = 3) |
XRGB2101010 |
5% |
5% |
0% |
5% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 3, PACKERS = 3) |
RGBA8888 |
10% |
5% |
0% |
5% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 3, PACKERS = 3) |
ABGR8888 |
10% |
5% |
0% |
5% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 3, PACKERS = 3) |
XBGR8888 |
10% |
5% |
0% |
5% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 3, PACKERS = 3) |
ARGB8888 |
10% |
5% |
0% |
5% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 3, PACKERS = 3) |
XRGB8888 |
10% |
5% |
0% |
5% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 3, PACKERS = 3) |
ABGR2101010 |
5% |
5% |
0% |
5% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 3, PACKERS = 3) |
XBGR2101010 |
5% |
5% |
0% |
5% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 3, PACKERS = 3) |
ARGB2101010 |
5% |
5% |
0% |
5% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 3, PACKERS = 3) |
XRGB2101010 |
5% |
5% |
0% |
5% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 3, PACKERS = 3) |
RGBA8888 |
10% |
5% |
0% |
5% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 3, PACKERS = 3) |
ABGR8888 |
10% |
5% |
0% |
5% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 3, PACKERS = 3) |
XBGR8888 |
10% |
5% |
0% |
5% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 3, PACKERS = 3) |
ARGB8888 |
10% |
5% |
0% |
5% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 3, PACKERS = 3) |
XRGB8888 |
10% |
5% |
0% |
5% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 3, PACKERS = 3) |
ABGR2101010 |
5% |
5% |
0% |
5% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 3, PACKERS = 3) |
XBGR2101010 |
5% |
5% |
0% |
5% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 3, PACKERS = 3) |
ARGB2101010 |
5% |
5% |
0% |
5% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 3, PACKERS = 3) |
XRGB2101010 |
5% |
5% |
0% |
5% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 3, PACKERS = 3) |
RGBA8888 |
10% |
5% |
0% |
5% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 3, PACKERS = 3) |
ABGR8888 |
10% |
5% |
0% |
5% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 3, PACKERS = 3) |
XBGR8888 |
10% |
5% |
0% |
5% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 3, PACKERS = 3) |
ARGB8888 |
10% |
5% |
0% |
5% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 3, PACKERS = 3) |
XRGB8888 |
10% |
5% |
0% |
5% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 4, PACKERS = 3) |
P010 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 4, PACKERS = 3) |
ABGR2101010 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 4, PACKERS = 3) |
XBGR2101010 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 4, PACKERS = 3) |
ARGB2101010 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 4, PACKERS = 3) |
XRGB2101010 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 4, PACKERS = 3) |
NV12 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 4, PACKERS = 3) |
RGBA8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 4, PACKERS = 3) |
ABGR8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 4, PACKERS = 3) |
XBGR8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 4, PACKERS = 3) |
ARGB8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 4, PACKERS = 3) |
XRGB8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 4, PACKERS = 3) |
RGB565 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 4, PACKERS = 3) |
ABGR16161616 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 4, PACKERS = 3) |
XBGR16161616 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 4, PACKERS = 3) |
ARGB16161616 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 4, PACKERS = 3) |
XRGB16161616 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 4, PACKERS = 3) |
ABGR16161616F |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 4, PACKERS = 3) |
XBGR16161616F |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 4, PACKERS = 3) |
ARGB16161616F |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 4, PACKERS = 3) |
XRGB16161616F |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4, PACKERS = 3) |
P010 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4, PACKERS = 3) |
ABGR2101010 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4, PACKERS = 3) |
XBGR2101010 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4, PACKERS = 3) |
ARGB2101010 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4, PACKERS = 3) |
XRGB2101010 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4, PACKERS = 3) |
NV12 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4, PACKERS = 3) |
RGBA8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4, PACKERS = 3) |
ABGR8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4, PACKERS = 3) |
XBGR8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4, PACKERS = 3) |
ARGB8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4, PACKERS = 3) |
XRGB8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4, PACKERS = 3) |
RGB565 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4, PACKERS = 3) |
ABGR16161616 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4, PACKERS = 3) |
XBGR16161616 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4, PACKERS = 3) |
ARGB16161616 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4, PACKERS = 3) |
XRGB16161616 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4, PACKERS = 3) |
ABGR16161616F |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4, PACKERS = 3) |
XBGR16161616F |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4, PACKERS = 3) |
ARGB16161616F |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4, PACKERS = 3) |
XRGB16161616F |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 4, PACKERS = 3) |
ABGR2101010 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 4, PACKERS = 3) |
XBGR2101010 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 4, PACKERS = 3) |
ARGB2101010 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 4, PACKERS = 3) |
XRGB2101010 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 4, PACKERS = 3) |
RGBA8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 4, PACKERS = 3) |
ABGR8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 4, PACKERS = 3) |
XBGR8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 4, PACKERS = 3) |
ARGB8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 4, PACKERS = 3) |
XRGB8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 4, PACKERS = 3) |
ABGR2101010 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 4, PACKERS = 3) |
XBGR2101010 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 4, PACKERS = 3) |
ARGB2101010 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 4, PACKERS = 3) |
XRGB2101010 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 4, PACKERS = 3) |
RGBA8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 4, PACKERS = 3) |
ABGR8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 4, PACKERS = 3) |
XBGR8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 4, PACKERS = 3) |
ARGB8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 4, PACKERS = 3) |
XRGB8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 4, PACKERS = 3) |
ABGR2101010 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 4, PACKERS = 3) |
XBGR2101010 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 4, PACKERS = 3) |
ARGB2101010 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 4, PACKERS = 3) |
XRGB2101010 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 4, PACKERS = 3) |
RGBA8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 4, PACKERS = 3) |
ABGR8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 4, PACKERS = 3) |
XBGR8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 4, PACKERS = 3) |
ARGB8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 4, PACKERS = 3) |
XRGB8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 4, PACKERS = 3) |
ABGR2101010 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 4, PACKERS = 3) |
XBGR2101010 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 4, PACKERS = 3) |
ARGB2101010 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 4, PACKERS = 3) |
XRGB2101010 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 4, PACKERS = 3) |
RGBA8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 4, PACKERS = 3) |
ABGR8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 4, PACKERS = 3) |
XBGR8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 4, PACKERS = 3) |
ARGB8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 4, PACKERS = 3) |
XRGB8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 4, PACKERS = 4) |
P010 |
10% |
5% |
0% |
5% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 4, PACKERS = 4) |
ABGR2101010 |
0% |
7% |
0% |
7% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 4, PACKERS = 4) |
XBGR2101010 |
0% |
7% |
0% |
7% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 4, PACKERS = 4) |
ARGB2101010 |
0% |
7% |
0% |
7% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 4, PACKERS = 4) |
XRGB2101010 |
0% |
7% |
0% |
7% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 4, PACKERS = 4) |
NV21 |
10% |
0% |
0% |
5% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 4, PACKERS = 4) |
NV12 |
10% |
7% |
0% |
7% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 4, PACKERS = 4) |
RGBA8888 |
15% |
7% |
0% |
7% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 4, PACKERS = 4) |
ABGR8888 |
15% |
7% |
0% |
7% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 4, PACKERS = 4) |
XBGR8888 |
15% |
7% |
0% |
7% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 4, PACKERS = 4) |
ARGB8888 |
15% |
7% |
0% |
7% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 4, PACKERS = 4) |
XRGB8888 |
15% |
7% |
0% |
7% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 4, PACKERS = 4) |
RGB565 |
15% |
7% |
0% |
7% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 4, PACKERS = 4) |
ABGR16161616 |
0% |
7% |
0% |
7% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 4, PACKERS = 4) |
XBGR16161616 |
0% |
7% |
0% |
7% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 4, PACKERS = 4) |
ARGB16161616 |
0% |
7% |
0% |
7% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 4, PACKERS = 4) |
XRGB16161616 |
0% |
7% |
0% |
7% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 4, PACKERS = 4) |
ABGR16161616F |
0% |
7% |
0% |
7% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 4, PACKERS = 4) |
XBGR16161616F |
0% |
7% |
0% |
7% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 4, PACKERS = 4) |
ARGB16161616F |
0% |
7% |
0% |
7% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 4, PACKERS = 4) |
XRGB16161616F |
0% |
7% |
0% |
7% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4, PACKERS = 4) |
P010 |
10% |
5% |
0% |
5% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4, PACKERS = 4) |
ABGR2101010 |
0% |
7% |
0% |
7% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4, PACKERS = 4) |
XBGR2101010 |
0% |
7% |
0% |
7% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4, PACKERS = 4) |
ARGB2101010 |
0% |
7% |
0% |
7% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4, PACKERS = 4) |
XRGB2101010 |
0% |
7% |
0% |
7% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4, PACKERS = 4) |
NV21 |
10% |
0% |
0% |
5% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4, PACKERS = 4) |
NV12 |
10% |
7% |
0% |
7% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4, PACKERS = 4) |
RGBA8888 |
15% |
7% |
0% |
7% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4, PACKERS = 4) |
ABGR8888 |
15% |
7% |
0% |
7% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4, PACKERS = 4) |
XBGR8888 |
15% |
7% |
0% |
7% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4, PACKERS = 4) |
ARGB8888 |
15% |
7% |
0% |
7% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4, PACKERS = 4) |
XRGB8888 |
15% |
7% |
0% |
7% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4, PACKERS = 4) |
RGB565 |
15% |
7% |
0% |
7% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4, PACKERS = 4) |
ABGR16161616 |
0% |
7% |
0% |
7% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4, PACKERS = 4) |
XBGR16161616 |
0% |
7% |
0% |
7% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4, PACKERS = 4) |
ARGB16161616 |
0% |
7% |
0% |
7% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4, PACKERS = 4) |
XRGB16161616 |
0% |
7% |
0% |
7% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4, PACKERS = 4) |
ABGR16161616F |
0% |
7% |
0% |
7% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4, PACKERS = 4) |
XBGR16161616F |
0% |
7% |
0% |
7% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4, PACKERS = 4) |
ARGB16161616F |
0% |
7% |
0% |
7% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4, PACKERS = 4) |
XRGB16161616F |
0% |
7% |
0% |
7% |
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4) |
P010 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4) |
ABGR2101010 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4) |
XBGR2101010 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4) |
ARGB2101010 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4) |
XRGB2101010 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4) |
NV12 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4) |
RGBA8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4) |
ABGR8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4) |
XBGR8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4) |
ARGB8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4) |
XRGB8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4) |
RGB565 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4) |
ABGR16161616 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4) |
XBGR16161616 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4) |
ARGB16161616 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4) |
XRGB16161616 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4) |
ABGR16161616F |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4) |
XBGR16161616F |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4) |
ARGB16161616F |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4) |
XRGB16161616F |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) |
P010 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) |
ABGR2101010 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) |
XBGR2101010 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) |
ARGB2101010 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) |
XRGB2101010 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) |
NV12 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) |
RGBA8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) |
ABGR8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) |
XBGR8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) |
ARGB8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) |
XRGB8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) |
RGB565 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) |
ABGR16161616 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) |
XBGR16161616 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) |
ARGB16161616 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) |
XRGB16161616 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) |
ABGR16161616F |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) |
XBGR16161616F |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) |
ARGB16161616F |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) |
XRGB16161616F |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, PIPE_XOR_BITS = 4) |
ABGR2101010 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, PIPE_XOR_BITS = 4) |
XBGR2101010 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, PIPE_XOR_BITS = 4) |
ARGB2101010 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, PIPE_XOR_BITS = 4) |
XRGB2101010 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, PIPE_XOR_BITS = 4) |
RGBA8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, PIPE_XOR_BITS = 4) |
ABGR8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, PIPE_XOR_BITS = 4) |
XBGR8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, PIPE_XOR_BITS = 4) |
ARGB8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, PIPE_XOR_BITS = 4) |
XRGB8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B) |
ABGR2101010 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B) |
XBGR2101010 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B) |
ARGB2101010 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B) |
XRGB2101010 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B) |
RGBA8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B) |
ABGR8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B) |
XBGR8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B) |
ARGB8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B) |
XRGB8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, PIPE_XOR_BITS = 4) |
ABGR2101010 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, PIPE_XOR_BITS = 4) |
XBGR2101010 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, PIPE_XOR_BITS = 4) |
ARGB2101010 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, PIPE_XOR_BITS = 4) |
XRGB2101010 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, PIPE_XOR_BITS = 4) |
RGBA8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, PIPE_XOR_BITS = 4) |
ABGR8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, PIPE_XOR_BITS = 4) |
XBGR8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, PIPE_XOR_BITS = 4) |
ARGB8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, PIPE_XOR_BITS = 4) |
XRGB8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B) |
ABGR2101010 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B) |
XBGR2101010 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B) |
ARGB2101010 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B) |
XRGB2101010 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B) |
RGBA8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B) |
ABGR8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B) |
XBGR8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B) |
ARGB8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B) |
XRGB8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, PIPE_XOR_BITS = 4) |
ABGR2101010 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, PIPE_XOR_BITS = 4) |
XBGR2101010 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, PIPE_XOR_BITS = 4) |
ARGB2101010 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, PIPE_XOR_BITS = 4) |
XRGB2101010 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, PIPE_XOR_BITS = 4) |
RGBA8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, PIPE_XOR_BITS = 4) |
ABGR8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, PIPE_XOR_BITS = 4) |
XBGR8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, PIPE_XOR_BITS = 4) |
ARGB8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, PIPE_XOR_BITS = 4) |
XRGB8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B) |
ABGR2101010 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B) |
XBGR2101010 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B) |
ARGB2101010 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B) |
XRGB2101010 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B) |
RGBA8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B) |
ABGR8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B) |
XBGR8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B) |
ARGB8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B) |
XRGB8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, PIPE_XOR_BITS = 4) |
ABGR2101010 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, PIPE_XOR_BITS = 4) |
XBGR2101010 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, PIPE_XOR_BITS = 4) |
ARGB2101010 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, PIPE_XOR_BITS = 4) |
XRGB2101010 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, PIPE_XOR_BITS = 4) |
RGBA8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, PIPE_XOR_BITS = 4) |
ABGR8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, PIPE_XOR_BITS = 4) |
XBGR8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, PIPE_XOR_BITS = 4) |
ARGB8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, PIPE_XOR_BITS = 4) |
XRGB8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B) |
ABGR2101010 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B) |
XBGR2101010 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B) |
ARGB2101010 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B) |
XRGB2101010 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B) |
RGBA8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B) |
ABGR8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B) |
XBGR8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B) |
ARGB8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B) |
XRGB8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 4, PACKERS = 4) |
ABGR2101010 |
0% |
7% |
0% |
7% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 4, PACKERS = 4) |
XBGR2101010 |
0% |
7% |
0% |
7% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 4, PACKERS = 4) |
ARGB2101010 |
0% |
7% |
0% |
7% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 4, PACKERS = 4) |
XRGB2101010 |
0% |
7% |
0% |
7% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 4, PACKERS = 4) |
RGBA8888 |
15% |
7% |
0% |
7% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 4, PACKERS = 4) |
ABGR8888 |
15% |
7% |
0% |
7% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 4, PACKERS = 4) |
XBGR8888 |
15% |
7% |
0% |
7% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 4, PACKERS = 4) |
ARGB8888 |
15% |
7% |
0% |
7% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 4, PACKERS = 4) |
XRGB8888 |
15% |
7% |
0% |
7% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 4, PACKERS = 4) |
ABGR2101010 |
0% |
7% |
0% |
7% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 4, PACKERS = 4) |
XBGR2101010 |
0% |
7% |
0% |
7% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 4, PACKERS = 4) |
ARGB2101010 |
0% |
7% |
0% |
7% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 4, PACKERS = 4) |
XRGB2101010 |
0% |
7% |
0% |
7% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 4, PACKERS = 4) |
RGBA8888 |
15% |
7% |
0% |
7% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 4, PACKERS = 4) |
ABGR8888 |
15% |
7% |
0% |
7% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 4, PACKERS = 4) |
XBGR8888 |
15% |
7% |
0% |
7% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 4, PACKERS = 4) |
ARGB8888 |
15% |
7% |
0% |
7% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 4, PACKERS = 4) |
XRGB8888 |
15% |
7% |
0% |
7% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 4, PACKERS = 4) |
ABGR2101010 |
0% |
5% |
0% |
5% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 4, PACKERS = 4) |
XBGR2101010 |
0% |
5% |
0% |
5% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 4, PACKERS = 4) |
ARGB2101010 |
0% |
5% |
0% |
5% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 4, PACKERS = 4) |
XRGB2101010 |
0% |
5% |
0% |
5% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 4, PACKERS = 4) |
RGBA8888 |
10% |
5% |
0% |
5% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 4, PACKERS = 4) |
ABGR8888 |
10% |
5% |
0% |
5% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 4, PACKERS = 4) |
XBGR8888 |
10% |
5% |
0% |
5% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 4, PACKERS = 4) |
ARGB8888 |
10% |
5% |
0% |
5% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 4, PACKERS = 4) |
XRGB8888 |
10% |
5% |
0% |
5% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 4, PACKERS = 4) |
ABGR2101010 |
0% |
5% |
0% |
5% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 4, PACKERS = 4) |
XBGR2101010 |
0% |
5% |
0% |
5% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 4, PACKERS = 4) |
ARGB2101010 |
0% |
5% |
0% |
5% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 4, PACKERS = 4) |
XRGB2101010 |
0% |
5% |
0% |
5% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 4, PACKERS = 4) |
RGBA8888 |
10% |
5% |
0% |
5% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 4, PACKERS = 4) |
ABGR8888 |
10% |
5% |
0% |
5% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 4, PACKERS = 4) |
XBGR8888 |
10% |
5% |
0% |
5% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 4, PACKERS = 4) |
ARGB8888 |
10% |
5% |
0% |
5% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 4, PACKERS = 4) |
XRGB8888 |
10% |
5% |
0% |
5% |
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 5) |
P010 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 5) |
ABGR2101010 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 5) |
XBGR2101010 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 5) |
ARGB2101010 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 5) |
XRGB2101010 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 5) |
NV12 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 5) |
RGBA8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 5) |
ABGR8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 5) |
XBGR8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 5) |
ARGB8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 5) |
XRGB8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 5) |
RGB565 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 5) |
ABGR16161616 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 5) |
XBGR16161616 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 5) |
ARGB16161616 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 5) |
XRGB16161616 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 5) |
ABGR16161616F |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 5) |
XBGR16161616F |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 5) |
ARGB16161616F |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 5) |
XRGB16161616F |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) |
P010 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) |
ABGR2101010 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) |
XBGR2101010 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) |
ARGB2101010 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) |
XRGB2101010 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) |
NV12 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) |
RGBA8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) |
ABGR8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) |
XBGR8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) |
ARGB8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) |
XRGB8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) |
RGB565 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) |
ABGR16161616 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) |
XBGR16161616 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) |
ARGB16161616 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) |
XRGB16161616 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) |
ABGR16161616F |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) |
XBGR16161616F |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) |
ARGB16161616F |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) |
XRGB16161616F |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, PIPE_XOR_BITS = 5) |
ABGR2101010 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, PIPE_XOR_BITS = 5) |
XBGR2101010 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, PIPE_XOR_BITS = 5) |
ARGB2101010 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, PIPE_XOR_BITS = 5) |
XRGB2101010 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, PIPE_XOR_BITS = 5) |
RGBA8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, PIPE_XOR_BITS = 5) |
ABGR8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, PIPE_XOR_BITS = 5) |
XBGR8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, PIPE_XOR_BITS = 5) |
ARGB8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, PIPE_XOR_BITS = 5) |
XRGB8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B) |
ABGR2101010 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B) |
XBGR2101010 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B) |
ARGB2101010 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B) |
XRGB2101010 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B) |
RGBA8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B) |
ABGR8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B) |
XBGR8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B) |
ARGB8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B) |
XRGB8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, PIPE_XOR_BITS = 5) |
ABGR2101010 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, PIPE_XOR_BITS = 5) |
XBGR2101010 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, PIPE_XOR_BITS = 5) |
ARGB2101010 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, PIPE_XOR_BITS = 5) |
XRGB2101010 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, PIPE_XOR_BITS = 5) |
RGBA8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, PIPE_XOR_BITS = 5) |
ABGR8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, PIPE_XOR_BITS = 5) |
XBGR8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, PIPE_XOR_BITS = 5) |
ARGB8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, PIPE_XOR_BITS = 5) |
XRGB8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B) |
ABGR2101010 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B) |
XBGR2101010 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B) |
ARGB2101010 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B) |
XRGB2101010 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B) |
RGBA8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B) |
ABGR8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B) |
XBGR8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B) |
ARGB8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B) |
XRGB8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, PIPE_XOR_BITS = 5) |
ABGR2101010 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, PIPE_XOR_BITS = 5) |
XBGR2101010 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, PIPE_XOR_BITS = 5) |
ARGB2101010 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, PIPE_XOR_BITS = 5) |
XRGB2101010 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, PIPE_XOR_BITS = 5) |
RGBA8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, PIPE_XOR_BITS = 5) |
ABGR8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, PIPE_XOR_BITS = 5) |
XBGR8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, PIPE_XOR_BITS = 5) |
ARGB8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, PIPE_XOR_BITS = 5) |
XRGB8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B) |
ABGR2101010 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B) |
XBGR2101010 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B) |
ARGB2101010 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B) |
XRGB2101010 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B) |
RGBA8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B) |
ABGR8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B) |
XBGR8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B) |
ARGB8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B) |
XRGB8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, PIPE_XOR_BITS = 5) |
ABGR2101010 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, PIPE_XOR_BITS = 5) |
XBGR2101010 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, PIPE_XOR_BITS = 5) |
ARGB2101010 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, PIPE_XOR_BITS = 5) |
XRGB2101010 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, PIPE_XOR_BITS = 5) |
RGBA8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, PIPE_XOR_BITS = 5) |
ABGR8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, PIPE_XOR_BITS = 5) |
XBGR8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, PIPE_XOR_BITS = 5) |
ARGB8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, PIPE_XOR_BITS = 5) |
XRGB8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B) |
ABGR2101010 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B) |
XBGR2101010 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B) |
ARGB2101010 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B) |
XRGB2101010 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B) |
RGBA8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B) |
ABGR8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B) |
XBGR8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B) |
ARGB8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B) |
XRGB8888 |
5% |
2% |
0% |
2% |
AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_S_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_MAX_COMPRESSED_BLOCK = 64B, PIPE_XOR_BITS = 2, BANK_XOR_BITS = 0, RB = 1, PIPE = 2) |
ABGR2101010 |
15% |
12% |
0% |
12% |
AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_S_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_MAX_COMPRESSED_BLOCK = 64B, PIPE_XOR_BITS = 2, BANK_XOR_BITS = 0, RB = 1, PIPE = 2) |
XBGR2101010 |
15% |
12% |
0% |
12% |
AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_S_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_MAX_COMPRESSED_BLOCK = 64B, PIPE_XOR_BITS = 2, BANK_XOR_BITS = 0, RB = 1, PIPE = 2) |
ARGB2101010 |
15% |
12% |
0% |
12% |
AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_S_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_MAX_COMPRESSED_BLOCK = 64B, PIPE_XOR_BITS = 2, BANK_XOR_BITS = 0, RB = 1, PIPE = 2) |
XRGB2101010 |
15% |
12% |
0% |
12% |
AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_S_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_MAX_COMPRESSED_BLOCK = 64B, PIPE_XOR_BITS = 2, BANK_XOR_BITS = 0, RB = 1, PIPE = 2) |
RGBA8888 |
25% |
12% |
0% |
12% |
AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_S_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_MAX_COMPRESSED_BLOCK = 64B, PIPE_XOR_BITS = 2, BANK_XOR_BITS = 0, RB = 1, PIPE = 2) |
ABGR8888 |
25% |
12% |
0% |
12% |
AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_S_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_MAX_COMPRESSED_BLOCK = 64B, PIPE_XOR_BITS = 2, BANK_XOR_BITS = 0, RB = 1, PIPE = 2) |
XBGR8888 |
25% |
12% |
0% |
12% |
AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_S_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_MAX_COMPRESSED_BLOCK = 64B, PIPE_XOR_BITS = 2, BANK_XOR_BITS = 0, RB = 1, PIPE = 2) |
ARGB8888 |
25% |
12% |
0% |
12% |
AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_S_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_MAX_COMPRESSED_BLOCK = 64B, PIPE_XOR_BITS = 2, BANK_XOR_BITS = 0, RB = 1, PIPE = 2) |
XRGB8888 |
25% |
12% |
0% |
12% |
AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_S_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, BANK_XOR_BITS = 0, RB = 1, PIPE = 2) |
ABGR2101010 |
10% |
7% |
0% |
7% |
AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_S_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, BANK_XOR_BITS = 0, RB = 1, PIPE = 2) |
XBGR2101010 |
10% |
7% |
0% |
7% |
AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_S_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, BANK_XOR_BITS = 0, RB = 1, PIPE = 2) |
ARGB2101010 |
10% |
7% |
0% |
7% |
AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_S_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, BANK_XOR_BITS = 0, RB = 1, PIPE = 2) |
XRGB2101010 |
10% |
7% |
0% |
7% |
AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_S_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, BANK_XOR_BITS = 0, RB = 1, PIPE = 2) |
RGBA8888 |
15% |
7% |
0% |
7% |
AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_S_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, BANK_XOR_BITS = 0, RB = 1, PIPE = 2) |
ABGR8888 |
15% |
7% |
0% |
7% |
AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_S_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, BANK_XOR_BITS = 0, RB = 1, PIPE = 2) |
XBGR8888 |
15% |
7% |
0% |
7% |
AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_S_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, BANK_XOR_BITS = 0, RB = 1, PIPE = 2) |
ARGB8888 |
15% |
7% |
0% |
7% |
AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_S_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, BANK_XOR_BITS = 0, RB = 1, PIPE = 2) |
XRGB8888 |
15% |
7% |
0% |
7% |