| LINEAR |
P010 |
87% |
49% |
0% |
49% |
| LINEAR |
ABGR2101010 |
90% |
86% |
0% |
86% |
| LINEAR |
XBGR2101010 |
90% |
86% |
0% |
86% |
| LINEAR |
ARGB2101010 |
90% |
86% |
0% |
86% |
| LINEAR |
XRGB2101010 |
90% |
86% |
0% |
86% |
| LINEAR |
NV21 |
3% |
0% |
0% |
2% |
| LINEAR |
NV12 |
94% |
54% |
0% |
54% |
| LINEAR |
RGBA8888 |
100% |
86% |
0% |
86% |
| LINEAR |
ABGR8888 |
100% |
86% |
0% |
86% |
| LINEAR |
XBGR8888 |
100% |
86% |
0% |
86% |
| LINEAR |
ARGB8888 |
100% |
100% |
100% |
100% |
| LINEAR |
XRGB8888 |
100% |
100% |
0% |
100% |
| LINEAR |
RGB565 |
100% |
84% |
0% |
84% |
| LINEAR |
ABGR16161616 |
90% |
82% |
0% |
82% |
| LINEAR |
XBGR16161616 |
90% |
82% |
0% |
82% |
| LINEAR |
ARGB16161616 |
90% |
82% |
0% |
82% |
| LINEAR |
XRGB16161616 |
90% |
82% |
0% |
82% |
| LINEAR |
ABGR16161616F |
90% |
79% |
0% |
79% |
| LINEAR |
XBGR16161616F |
90% |
79% |
0% |
79% |
| LINEAR |
ARGB16161616F |
90% |
79% |
0% |
79% |
| LINEAR |
XRGB16161616F |
90% |
79% |
0% |
79% |
| AMD(TILE_VERSION = unknown, TILE = unknown) |
P010 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown) |
ABGR2101010 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown) |
XBGR2101010 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown) |
ARGB2101010 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown) |
XRGB2101010 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown) |
NV12 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown) |
RGBA8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown) |
ABGR8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown) |
XBGR8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown) |
ARGB8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown) |
XRGB8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown) |
RGB565 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown) |
ABGR16161616 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown) |
XBGR16161616 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown) |
ARGB16161616 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown) |
XRGB16161616 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown) |
ABGR16161616F |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown) |
XBGR16161616F |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown) |
ARGB16161616F |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown) |
XRGB16161616F |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown) |
P010 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown) |
ABGR2101010 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown) |
XBGR2101010 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown) |
ARGB2101010 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown) |
XRGB2101010 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown) |
NV12 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown) |
RGBA8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown) |
ABGR8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown) |
XBGR8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown) |
ARGB8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown) |
XRGB8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown) |
RGB565 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown) |
ABGR16161616 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown) |
XBGR16161616 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown) |
ARGB16161616 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown) |
XRGB16161616 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown) |
ABGR16161616F |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown) |
XBGR16161616F |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown) |
ARGB16161616F |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown) |
XRGB16161616F |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown) |
P010 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown) |
ABGR2101010 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown) |
XBGR2101010 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown) |
ARGB2101010 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown) |
XRGB2101010 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown) |
NV12 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown) |
RGBA8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown) |
ABGR8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown) |
XBGR8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown) |
ARGB8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown) |
XRGB8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown) |
RGB565 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown) |
ABGR16161616 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown) |
XBGR16161616 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown) |
ARGB16161616 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown) |
XRGB16161616 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown) |
ABGR16161616F |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown) |
XBGR16161616F |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown) |
ARGB16161616F |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown) |
XRGB16161616F |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown) |
P010 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown) |
ABGR2101010 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown) |
XBGR2101010 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown) |
ARGB2101010 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown) |
XRGB2101010 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown) |
NV12 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown) |
RGBA8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown) |
ABGR8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown) |
XBGR8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown) |
ARGB8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown) |
XRGB8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown) |
RGB565 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown) |
ABGR16161616 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown) |
XBGR16161616 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown) |
ARGB16161616 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown) |
XRGB16161616 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown) |
ABGR16161616F |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown) |
XBGR16161616F |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown) |
ARGB16161616F |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown) |
XRGB16161616F |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_S) |
P010 |
55% |
32% |
0% |
32% |
| AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_S) |
ABGR2101010 |
58% |
37% |
0% |
37% |
| AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_S) |
XBGR2101010 |
58% |
37% |
0% |
37% |
| AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_S) |
ARGB2101010 |
58% |
37% |
0% |
37% |
| AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_S) |
XRGB2101010 |
58% |
37% |
0% |
37% |
| AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_S) |
NV21 |
3% |
0% |
0% |
2% |
| AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_S) |
NV12 |
61% |
37% |
0% |
37% |
| AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_S) |
RGBA8888 |
68% |
37% |
0% |
37% |
| AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_S) |
ABGR8888 |
68% |
37% |
0% |
37% |
| AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_S) |
XBGR8888 |
68% |
37% |
0% |
37% |
| AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_S) |
ARGB8888 |
68% |
37% |
0% |
37% |
| AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_S) |
XRGB8888 |
68% |
37% |
0% |
37% |
| AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_S) |
RGB565 |
68% |
37% |
0% |
37% |
| AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_S) |
ABGR16161616 |
58% |
37% |
0% |
37% |
| AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_S) |
XBGR16161616 |
58% |
37% |
0% |
37% |
| AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_S) |
ARGB16161616 |
58% |
37% |
0% |
37% |
| AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_S) |
XRGB16161616 |
58% |
37% |
0% |
37% |
| AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_S) |
ABGR16161616F |
58% |
37% |
0% |
37% |
| AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_S) |
XBGR16161616F |
58% |
37% |
0% |
37% |
| AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_S) |
ARGB16161616F |
58% |
37% |
0% |
37% |
| AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_S) |
XRGB16161616F |
58% |
37% |
0% |
37% |
| AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_D) |
ABGR2101010 |
0% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_D) |
XBGR2101010 |
0% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_D) |
ARGB2101010 |
0% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_D) |
XRGB2101010 |
0% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_D) |
RGBA8888 |
0% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_D) |
ABGR8888 |
0% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_D) |
XBGR8888 |
0% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_D) |
ARGB8888 |
0% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_D) |
XRGB8888 |
0% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_D) |
RGB565 |
0% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_D) |
ABGR16161616 |
58% |
39% |
0% |
39% |
| AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_D) |
XBGR16161616 |
58% |
39% |
0% |
39% |
| AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_D) |
ARGB16161616 |
58% |
39% |
0% |
39% |
| AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_D) |
XRGB16161616 |
58% |
39% |
0% |
39% |
| AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_D) |
ABGR16161616F |
58% |
39% |
0% |
39% |
| AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_D) |
XBGR16161616F |
58% |
39% |
0% |
39% |
| AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_D) |
ARGB16161616F |
58% |
39% |
0% |
39% |
| AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_D) |
XRGB16161616F |
58% |
39% |
0% |
39% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_D) |
ABGR16161616 |
26% |
14% |
0% |
14% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_D) |
XBGR16161616 |
26% |
14% |
0% |
14% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_D) |
ARGB16161616 |
26% |
14% |
0% |
14% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_D) |
XRGB16161616 |
26% |
14% |
0% |
14% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_D) |
ABGR16161616F |
26% |
14% |
0% |
14% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_D) |
XBGR16161616F |
26% |
14% |
0% |
14% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_D) |
ARGB16161616F |
26% |
14% |
0% |
14% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_D) |
XRGB16161616F |
26% |
14% |
0% |
14% |
| AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 64B) |
P010 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 64B) |
ABGR2101010 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 64B) |
XBGR2101010 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 64B) |
ARGB2101010 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 64B) |
XRGB2101010 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 64B) |
NV12 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 64B) |
RGBA8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 64B) |
ABGR8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 64B) |
XBGR8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 64B) |
ARGB8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 64B) |
XRGB8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 64B) |
RGB565 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 64B) |
ABGR16161616 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 64B) |
XBGR16161616 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 64B) |
ARGB16161616 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 64B) |
XRGB16161616 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 64B) |
ABGR16161616F |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 64B) |
XBGR16161616F |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 64B) |
ARGB16161616F |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 64B) |
XRGB16161616F |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 64B) |
P010 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 64B) |
ABGR2101010 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 64B) |
XBGR2101010 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 64B) |
ARGB2101010 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 64B) |
XRGB2101010 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 64B) |
NV12 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 64B) |
RGBA8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 64B) |
ABGR8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 64B) |
XBGR8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 64B) |
ARGB8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 64B) |
XRGB8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 64B) |
RGB565 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 64B) |
ABGR16161616 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 64B) |
XBGR16161616 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 64B) |
ARGB16161616 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 64B) |
XRGB16161616 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 64B) |
ABGR16161616F |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 64B) |
XBGR16161616F |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 64B) |
ARGB16161616F |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 64B) |
XRGB16161616F |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 64B) |
P010 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 64B) |
ABGR2101010 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 64B) |
XBGR2101010 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 64B) |
ARGB2101010 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 64B) |
XRGB2101010 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 64B) |
NV12 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 64B) |
RGBA8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 64B) |
ABGR8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 64B) |
XBGR8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 64B) |
ARGB8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 64B) |
XRGB8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 64B) |
RGB565 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 64B) |
ABGR16161616 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 64B) |
XBGR16161616 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 64B) |
ARGB16161616 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 64B) |
XRGB16161616 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 64B) |
ABGR16161616F |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 64B) |
XBGR16161616F |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 64B) |
ARGB16161616F |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 64B) |
XRGB16161616F |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 64B) |
P010 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 64B) |
ABGR2101010 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 64B) |
XBGR2101010 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 64B) |
ARGB2101010 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 64B) |
XRGB2101010 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 64B) |
NV12 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 64B) |
RGBA8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 64B) |
ABGR8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 64B) |
XBGR8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 64B) |
ARGB8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 64B) |
XRGB8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 64B) |
RGB565 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 64B) |
ABGR16161616 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 64B) |
XBGR16161616 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 64B) |
ARGB16161616 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 64B) |
XRGB16161616 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 64B) |
ABGR16161616F |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 64B) |
XBGR16161616F |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 64B) |
ARGB16161616F |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 64B) |
XRGB16161616F |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 128B) |
P010 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 128B) |
ABGR2101010 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 128B) |
XBGR2101010 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 128B) |
ARGB2101010 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 128B) |
XRGB2101010 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 128B) |
NV12 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 128B) |
RGBA8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 128B) |
ABGR8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 128B) |
XBGR8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 128B) |
ARGB8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 128B) |
XRGB8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 128B) |
RGB565 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 128B) |
ABGR16161616 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 128B) |
XBGR16161616 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 128B) |
ARGB16161616 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 128B) |
XRGB16161616 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 128B) |
ABGR16161616F |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 128B) |
XBGR16161616F |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 128B) |
ARGB16161616F |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 128B) |
XRGB16161616F |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 128B) |
P010 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 128B) |
ABGR2101010 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 128B) |
XBGR2101010 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 128B) |
ARGB2101010 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 128B) |
XRGB2101010 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 128B) |
NV12 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 128B) |
RGBA8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 128B) |
ABGR8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 128B) |
XBGR8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 128B) |
ARGB8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 128B) |
XRGB8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 128B) |
RGB565 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 128B) |
ABGR16161616 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 128B) |
XBGR16161616 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 128B) |
ARGB16161616 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 128B) |
XRGB16161616 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 128B) |
ABGR16161616F |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 128B) |
XBGR16161616F |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 128B) |
ARGB16161616F |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 128B) |
XRGB16161616F |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 128B) |
P010 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 128B) |
ABGR2101010 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 128B) |
XBGR2101010 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 128B) |
ARGB2101010 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 128B) |
XRGB2101010 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 128B) |
NV12 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 128B) |
RGBA8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 128B) |
ABGR8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 128B) |
XBGR8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 128B) |
ARGB8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 128B) |
XRGB8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 128B) |
RGB565 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 128B) |
ABGR16161616 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 128B) |
XBGR16161616 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 128B) |
ARGB16161616 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 128B) |
XRGB16161616 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 128B) |
ABGR16161616F |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 128B) |
XBGR16161616F |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 128B) |
ARGB16161616F |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 128B) |
XRGB16161616F |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 128B) |
P010 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 128B) |
ABGR2101010 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 128B) |
XBGR2101010 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 128B) |
ARGB2101010 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 128B) |
XRGB2101010 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 128B) |
NV12 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 128B) |
RGBA8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 128B) |
ABGR8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 128B) |
XBGR8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 128B) |
ARGB8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 128B) |
XRGB8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 128B) |
RGB565 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 128B) |
ABGR16161616 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 128B) |
XBGR16161616 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 128B) |
ARGB16161616 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 128B) |
XRGB16161616 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 128B) |
ABGR16161616F |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 128B) |
XBGR16161616F |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 128B) |
ARGB16161616F |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 128B) |
XRGB16161616F |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 256B) |
P010 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 256B) |
ABGR2101010 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 256B) |
XBGR2101010 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 256B) |
ARGB2101010 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 256B) |
XRGB2101010 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 256B) |
NV12 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 256B) |
RGBA8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 256B) |
ABGR8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 256B) |
XBGR8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 256B) |
ARGB8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 256B) |
XRGB8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 256B) |
RGB565 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 256B) |
ABGR16161616 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 256B) |
XBGR16161616 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 256B) |
ARGB16161616 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 256B) |
XRGB16161616 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 256B) |
ABGR16161616F |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 256B) |
XBGR16161616F |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 256B) |
ARGB16161616F |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 256B) |
XRGB16161616F |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 256B) |
P010 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 256B) |
ABGR2101010 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 256B) |
XBGR2101010 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 256B) |
ARGB2101010 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 256B) |
XRGB2101010 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 256B) |
NV12 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 256B) |
RGBA8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 256B) |
ABGR8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 256B) |
XBGR8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 256B) |
ARGB8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 256B) |
XRGB8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 256B) |
RGB565 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 256B) |
ABGR16161616 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 256B) |
XBGR16161616 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 256B) |
ARGB16161616 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 256B) |
XRGB16161616 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 256B) |
ABGR16161616F |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 256B) |
XBGR16161616F |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 256B) |
ARGB16161616F |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 256B) |
XRGB16161616F |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 256B) |
P010 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 256B) |
ABGR2101010 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 256B) |
XBGR2101010 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 256B) |
ARGB2101010 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 256B) |
XRGB2101010 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 256B) |
NV12 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 256B) |
RGBA8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 256B) |
ABGR8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 256B) |
XBGR8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 256B) |
ARGB8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 256B) |
XRGB8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 256B) |
RGB565 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 256B) |
ABGR16161616 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 256B) |
XBGR16161616 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 256B) |
ARGB16161616 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 256B) |
XRGB16161616 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 256B) |
ABGR16161616F |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 256B) |
XBGR16161616F |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 256B) |
ARGB16161616F |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 256B) |
XRGB16161616F |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 256B) |
P010 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 256B) |
ABGR2101010 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 256B) |
XBGR2101010 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 256B) |
ARGB2101010 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 256B) |
XRGB2101010 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 256B) |
NV12 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 256B) |
RGBA8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 256B) |
ABGR8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 256B) |
XBGR8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 256B) |
ARGB8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 256B) |
XRGB8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 256B) |
RGB565 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 256B) |
ABGR16161616 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 256B) |
XBGR16161616 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 256B) |
ARGB16161616 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 256B) |
XRGB16161616 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 256B) |
ABGR16161616F |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 256B) |
XBGR16161616F |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 256B) |
ARGB16161616F |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 256B) |
XRGB16161616F |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 2, BANK_XOR_BITS = 0) |
P010 |
13% |
7% |
0% |
7% |
| AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 2, BANK_XOR_BITS = 0) |
ABGR2101010 |
19% |
11% |
0% |
11% |
| AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 2, BANK_XOR_BITS = 0) |
XBGR2101010 |
19% |
11% |
0% |
11% |
| AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 2, BANK_XOR_BITS = 0) |
ARGB2101010 |
19% |
11% |
0% |
11% |
| AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 2, BANK_XOR_BITS = 0) |
XRGB2101010 |
19% |
11% |
0% |
11% |
| AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 2, BANK_XOR_BITS = 0) |
NV12 |
19% |
11% |
0% |
11% |
| AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 2, BANK_XOR_BITS = 0) |
RGBA8888 |
19% |
11% |
0% |
11% |
| AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 2, BANK_XOR_BITS = 0) |
ABGR8888 |
19% |
11% |
0% |
11% |
| AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 2, BANK_XOR_BITS = 0) |
XBGR8888 |
19% |
11% |
0% |
11% |
| AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 2, BANK_XOR_BITS = 0) |
ARGB8888 |
19% |
11% |
0% |
11% |
| AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 2, BANK_XOR_BITS = 0) |
XRGB8888 |
19% |
11% |
0% |
11% |
| AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 2, BANK_XOR_BITS = 0) |
RGB565 |
19% |
11% |
0% |
11% |
| AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 2, BANK_XOR_BITS = 0) |
ABGR16161616 |
19% |
11% |
0% |
11% |
| AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 2, BANK_XOR_BITS = 0) |
XBGR16161616 |
19% |
11% |
0% |
11% |
| AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 2, BANK_XOR_BITS = 0) |
ARGB16161616 |
19% |
11% |
0% |
11% |
| AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 2, BANK_XOR_BITS = 0) |
XRGB16161616 |
19% |
11% |
0% |
11% |
| AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 2, BANK_XOR_BITS = 0) |
ABGR16161616F |
19% |
11% |
0% |
11% |
| AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 2, BANK_XOR_BITS = 0) |
XBGR16161616F |
19% |
11% |
0% |
11% |
| AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 2, BANK_XOR_BITS = 0) |
ARGB16161616F |
19% |
11% |
0% |
11% |
| AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 2, BANK_XOR_BITS = 0) |
XRGB16161616F |
19% |
11% |
0% |
11% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 2, PACKERS = 0) |
P010 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 2, PACKERS = 0) |
ABGR2101010 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 2, PACKERS = 0) |
XBGR2101010 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 2, PACKERS = 0) |
ARGB2101010 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 2, PACKERS = 0) |
XRGB2101010 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 2, PACKERS = 0) |
NV12 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 2, PACKERS = 0) |
RGBA8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 2, PACKERS = 0) |
ABGR8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 2, PACKERS = 0) |
XBGR8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 2, PACKERS = 0) |
ARGB8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 2, PACKERS = 0) |
XRGB8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 2, PACKERS = 0) |
RGB565 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 2, PACKERS = 0) |
ABGR16161616 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 2, PACKERS = 0) |
XBGR16161616 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 2, PACKERS = 0) |
ARGB16161616 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 2, PACKERS = 0) |
XRGB16161616 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 2, PACKERS = 0) |
ABGR16161616F |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 2, PACKERS = 0) |
XBGR16161616F |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 2, PACKERS = 0) |
ARGB16161616F |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 2, PACKERS = 0) |
XRGB16161616F |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_D_X, PIPE_XOR_BITS = 2, BANK_XOR_BITS = 0) |
ABGR16161616 |
19% |
11% |
0% |
11% |
| AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_D_X, PIPE_XOR_BITS = 2, BANK_XOR_BITS = 0) |
XBGR16161616 |
19% |
11% |
0% |
11% |
| AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_D_X, PIPE_XOR_BITS = 2, BANK_XOR_BITS = 0) |
ARGB16161616 |
19% |
11% |
0% |
11% |
| AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_D_X, PIPE_XOR_BITS = 2, BANK_XOR_BITS = 0) |
XRGB16161616 |
19% |
11% |
0% |
11% |
| AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_D_X, PIPE_XOR_BITS = 2, BANK_XOR_BITS = 0) |
ABGR16161616F |
19% |
11% |
0% |
11% |
| AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_D_X, PIPE_XOR_BITS = 2, BANK_XOR_BITS = 0) |
XBGR16161616F |
19% |
11% |
0% |
11% |
| AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_D_X, PIPE_XOR_BITS = 2, BANK_XOR_BITS = 0) |
ARGB16161616F |
19% |
11% |
0% |
11% |
| AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_D_X, PIPE_XOR_BITS = 2, BANK_XOR_BITS = 0) |
XRGB16161616F |
19% |
11% |
0% |
11% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2, PACKERS = 0) |
P010 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2, PACKERS = 0) |
ABGR2101010 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2, PACKERS = 0) |
XBGR2101010 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2, PACKERS = 0) |
ARGB2101010 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2, PACKERS = 0) |
XRGB2101010 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2, PACKERS = 0) |
NV12 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2, PACKERS = 0) |
RGBA8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2, PACKERS = 0) |
ABGR8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2, PACKERS = 0) |
XBGR8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2, PACKERS = 0) |
ARGB8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2, PACKERS = 0) |
XRGB8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2, PACKERS = 0) |
RGB565 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2, PACKERS = 0) |
ABGR16161616 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2, PACKERS = 0) |
XBGR16161616 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2, PACKERS = 0) |
ARGB16161616 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2, PACKERS = 0) |
XRGB16161616 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2, PACKERS = 0) |
ABGR16161616F |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2, PACKERS = 0) |
XBGR16161616F |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2, PACKERS = 0) |
ARGB16161616F |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2, PACKERS = 0) |
XRGB16161616F |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_S_X, DCC, DCC_INDEPENDENT_64B, DCC_MAX_COMPRESSED_BLOCK = 64B, PIPE_XOR_BITS = 2, BANK_XOR_BITS = 0, RB = 0) |
ABGR2101010 |
19% |
11% |
0% |
11% |
| AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_S_X, DCC, DCC_INDEPENDENT_64B, DCC_MAX_COMPRESSED_BLOCK = 64B, PIPE_XOR_BITS = 2, BANK_XOR_BITS = 0, RB = 0) |
XBGR2101010 |
19% |
11% |
0% |
11% |
| AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_S_X, DCC, DCC_INDEPENDENT_64B, DCC_MAX_COMPRESSED_BLOCK = 64B, PIPE_XOR_BITS = 2, BANK_XOR_BITS = 0, RB = 0) |
ARGB2101010 |
19% |
11% |
0% |
11% |
| AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_S_X, DCC, DCC_INDEPENDENT_64B, DCC_MAX_COMPRESSED_BLOCK = 64B, PIPE_XOR_BITS = 2, BANK_XOR_BITS = 0, RB = 0) |
XRGB2101010 |
19% |
11% |
0% |
11% |
| AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_S_X, DCC, DCC_INDEPENDENT_64B, DCC_MAX_COMPRESSED_BLOCK = 64B, PIPE_XOR_BITS = 2, BANK_XOR_BITS = 0, RB = 0) |
RGBA8888 |
19% |
11% |
0% |
11% |
| AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_S_X, DCC, DCC_INDEPENDENT_64B, DCC_MAX_COMPRESSED_BLOCK = 64B, PIPE_XOR_BITS = 2, BANK_XOR_BITS = 0, RB = 0) |
ABGR8888 |
19% |
11% |
0% |
11% |
| AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_S_X, DCC, DCC_INDEPENDENT_64B, DCC_MAX_COMPRESSED_BLOCK = 64B, PIPE_XOR_BITS = 2, BANK_XOR_BITS = 0, RB = 0) |
XBGR8888 |
19% |
11% |
0% |
11% |
| AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_S_X, DCC, DCC_INDEPENDENT_64B, DCC_MAX_COMPRESSED_BLOCK = 64B, PIPE_XOR_BITS = 2, BANK_XOR_BITS = 0, RB = 0) |
ARGB8888 |
19% |
11% |
0% |
11% |
| AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_S_X, DCC, DCC_INDEPENDENT_64B, DCC_MAX_COMPRESSED_BLOCK = 64B, PIPE_XOR_BITS = 2, BANK_XOR_BITS = 0, RB = 0) |
XRGB8888 |
19% |
11% |
0% |
11% |
| AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_S_X, DCC, DCC_INDEPENDENT_64B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, BANK_XOR_BITS = 0, RB = 0) |
ABGR2101010 |
13% |
7% |
0% |
7% |
| AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_S_X, DCC, DCC_INDEPENDENT_64B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, BANK_XOR_BITS = 0, RB = 0) |
XBGR2101010 |
13% |
7% |
0% |
7% |
| AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_S_X, DCC, DCC_INDEPENDENT_64B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, BANK_XOR_BITS = 0, RB = 0) |
ARGB2101010 |
13% |
7% |
0% |
7% |
| AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_S_X, DCC, DCC_INDEPENDENT_64B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, BANK_XOR_BITS = 0, RB = 0) |
XRGB2101010 |
13% |
7% |
0% |
7% |
| AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_S_X, DCC, DCC_INDEPENDENT_64B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, BANK_XOR_BITS = 0, RB = 0) |
RGBA8888 |
13% |
7% |
0% |
7% |
| AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_S_X, DCC, DCC_INDEPENDENT_64B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, BANK_XOR_BITS = 0, RB = 0) |
ABGR8888 |
13% |
7% |
0% |
7% |
| AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_S_X, DCC, DCC_INDEPENDENT_64B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, BANK_XOR_BITS = 0, RB = 0) |
XBGR8888 |
13% |
7% |
0% |
7% |
| AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_S_X, DCC, DCC_INDEPENDENT_64B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, BANK_XOR_BITS = 0, RB = 0) |
ARGB8888 |
13% |
7% |
0% |
7% |
| AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_S_X, DCC, DCC_INDEPENDENT_64B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, BANK_XOR_BITS = 0, RB = 0) |
XRGB8888 |
13% |
7% |
0% |
7% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, PACKERS = 0) |
ABGR2101010 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, PACKERS = 0) |
XBGR2101010 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, PACKERS = 0) |
ARGB2101010 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, PACKERS = 0) |
XRGB2101010 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, PACKERS = 0) |
RGBA8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, PACKERS = 0) |
ABGR8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, PACKERS = 0) |
XBGR8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, PACKERS = 0) |
ARGB8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, PACKERS = 0) |
XRGB8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, PACKERS = 0) |
ABGR2101010 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, PACKERS = 0) |
XBGR2101010 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, PACKERS = 0) |
ARGB2101010 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, PACKERS = 0) |
XRGB2101010 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, PACKERS = 0) |
RGBA8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, PACKERS = 0) |
ABGR8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, PACKERS = 0) |
XBGR8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, PACKERS = 0) |
ARGB8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, PACKERS = 0) |
XRGB8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, PACKERS = 0) |
ABGR2101010 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, PACKERS = 0) |
XBGR2101010 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, PACKERS = 0) |
ARGB2101010 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, PACKERS = 0) |
XRGB2101010 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, PACKERS = 0) |
RGBA8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, PACKERS = 0) |
ABGR8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, PACKERS = 0) |
XBGR8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, PACKERS = 0) |
ARGB8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, PACKERS = 0) |
XRGB8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, PACKERS = 0) |
ABGR2101010 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, PACKERS = 0) |
XBGR2101010 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, PACKERS = 0) |
ARGB2101010 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, PACKERS = 0) |
XRGB2101010 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, PACKERS = 0) |
RGBA8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, PACKERS = 0) |
ABGR8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, PACKERS = 0) |
XBGR8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, PACKERS = 0) |
ARGB8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, PACKERS = 0) |
XRGB8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 3) |
P010 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 3) |
ABGR2101010 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 3) |
XBGR2101010 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 3) |
ARGB2101010 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 3) |
XRGB2101010 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 3) |
NV12 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 3) |
RGBA8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 3) |
ABGR8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 3) |
XBGR8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 3) |
ARGB8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 3) |
XRGB8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 3) |
RGB565 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 3) |
ABGR16161616 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 3) |
XBGR16161616 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 3) |
ARGB16161616 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 3) |
XRGB16161616 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 3) |
ABGR16161616F |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 3) |
XBGR16161616F |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 3) |
ARGB16161616F |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 3) |
XRGB16161616F |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 3) |
P010 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 3) |
ABGR2101010 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 3) |
XBGR2101010 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 3) |
ARGB2101010 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 3) |
XRGB2101010 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 3) |
NV12 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 3) |
RGBA8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 3) |
ABGR8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 3) |
XBGR8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 3) |
ARGB8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 3) |
XRGB8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 3) |
RGB565 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 3) |
ABGR16161616 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 3) |
XBGR16161616 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 3) |
ARGB16161616 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 3) |
XRGB16161616 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 3) |
ABGR16161616F |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 3) |
XBGR16161616F |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 3) |
ARGB16161616F |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 3) |
XRGB16161616F |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 3) |
ABGR2101010 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 3) |
XBGR2101010 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 3) |
ARGB2101010 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 3) |
XRGB2101010 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 3) |
RGBA8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 3) |
ABGR8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 3) |
XBGR8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 3) |
ARGB8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 3) |
XRGB8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 3) |
ABGR2101010 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 3) |
XBGR2101010 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 3) |
ARGB2101010 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 3) |
XRGB2101010 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 3) |
RGBA8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 3) |
ABGR8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 3) |
XBGR8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 3) |
ARGB8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 3) |
XRGB8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 4) |
P010 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 4) |
ABGR2101010 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 4) |
XBGR2101010 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 4) |
ARGB2101010 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 4) |
XRGB2101010 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 4) |
NV12 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 4) |
RGBA8888 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 4) |
ABGR8888 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 4) |
XBGR8888 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 4) |
ARGB8888 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 4) |
XRGB8888 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 4) |
RGB565 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 4) |
ABGR16161616 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 4) |
XBGR16161616 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 4) |
ARGB16161616 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 4) |
XRGB16161616 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 4) |
ABGR16161616F |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 4) |
XBGR16161616F |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 4) |
ARGB16161616F |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 4) |
XRGB16161616F |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4) |
P010 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4) |
ABGR2101010 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4) |
XBGR2101010 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4) |
ARGB2101010 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4) |
XRGB2101010 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4) |
NV12 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4) |
RGBA8888 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4) |
ABGR8888 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4) |
XBGR8888 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4) |
ARGB8888 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4) |
XRGB8888 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4) |
RGB565 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4) |
ABGR16161616 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4) |
XBGR16161616 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4) |
ARGB16161616 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4) |
XRGB16161616 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4) |
ABGR16161616F |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4) |
XBGR16161616F |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4) |
ARGB16161616F |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4) |
XRGB16161616F |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 4) |
ABGR2101010 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 4) |
XBGR2101010 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 4) |
ARGB2101010 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 4) |
XRGB2101010 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 4) |
RGBA8888 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 4) |
ABGR8888 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 4) |
XBGR8888 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 4) |
ARGB8888 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 4) |
XRGB8888 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 4) |
ABGR2101010 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 4) |
XBGR2101010 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 4) |
ARGB2101010 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 4) |
XRGB2101010 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 4) |
RGBA8888 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 4) |
ABGR8888 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 4) |
XBGR8888 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 4) |
ARGB8888 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 4) |
XRGB8888 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_D_X, PIPE_XOR_BITS = 4, BANK_XOR_BITS = 4) |
ABGR2101010 |
0% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_D_X, PIPE_XOR_BITS = 4, BANK_XOR_BITS = 4) |
XBGR2101010 |
0% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_D_X, PIPE_XOR_BITS = 4, BANK_XOR_BITS = 4) |
ARGB2101010 |
0% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_D_X, PIPE_XOR_BITS = 4, BANK_XOR_BITS = 4) |
XRGB2101010 |
0% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_D_X, PIPE_XOR_BITS = 4, BANK_XOR_BITS = 4) |
RGBA8888 |
0% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_D_X, PIPE_XOR_BITS = 4, BANK_XOR_BITS = 4) |
ABGR8888 |
0% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_D_X, PIPE_XOR_BITS = 4, BANK_XOR_BITS = 4) |
XBGR8888 |
0% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_D_X, PIPE_XOR_BITS = 4, BANK_XOR_BITS = 4) |
ARGB8888 |
0% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_D_X, PIPE_XOR_BITS = 4, BANK_XOR_BITS = 4) |
XRGB8888 |
0% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_D_X, PIPE_XOR_BITS = 4, BANK_XOR_BITS = 4) |
RGB565 |
0% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_D_X, PIPE_XOR_BITS = 4, BANK_XOR_BITS = 4) |
ABGR16161616 |
0% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_D_X, PIPE_XOR_BITS = 4, BANK_XOR_BITS = 4) |
XBGR16161616 |
0% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_D_X, PIPE_XOR_BITS = 4, BANK_XOR_BITS = 4) |
ARGB16161616 |
0% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_D_X, PIPE_XOR_BITS = 4, BANK_XOR_BITS = 4) |
XRGB16161616 |
0% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_D_X, PIPE_XOR_BITS = 4, BANK_XOR_BITS = 4) |
ABGR16161616F |
0% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_D_X, PIPE_XOR_BITS = 4, BANK_XOR_BITS = 4) |
XBGR16161616F |
0% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_D_X, PIPE_XOR_BITS = 4, BANK_XOR_BITS = 4) |
ARGB16161616F |
0% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_D_X, PIPE_XOR_BITS = 4, BANK_XOR_BITS = 4) |
XRGB16161616F |
0% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 2, PACKERS = 1) |
P010 |
3% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 2, PACKERS = 1) |
ABGR2101010 |
3% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 2, PACKERS = 1) |
XBGR2101010 |
3% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 2, PACKERS = 1) |
ARGB2101010 |
3% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 2, PACKERS = 1) |
XRGB2101010 |
3% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 2, PACKERS = 1) |
NV12 |
3% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 2, PACKERS = 1) |
RGBA8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 2, PACKERS = 1) |
ABGR8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 2, PACKERS = 1) |
XBGR8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 2, PACKERS = 1) |
ARGB8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 2, PACKERS = 1) |
XRGB8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 2, PACKERS = 1) |
RGB565 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 2, PACKERS = 1) |
ABGR16161616 |
3% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 2, PACKERS = 1) |
XBGR16161616 |
3% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 2, PACKERS = 1) |
ARGB16161616 |
3% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 2, PACKERS = 1) |
XRGB16161616 |
3% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 2, PACKERS = 1) |
ABGR16161616F |
3% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 2, PACKERS = 1) |
XBGR16161616F |
3% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 2, PACKERS = 1) |
ARGB16161616F |
3% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 2, PACKERS = 1) |
XRGB16161616F |
3% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2, PACKERS = 1) |
P010 |
3% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2, PACKERS = 1) |
ABGR2101010 |
3% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2, PACKERS = 1) |
XBGR2101010 |
3% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2, PACKERS = 1) |
ARGB2101010 |
3% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2, PACKERS = 1) |
XRGB2101010 |
3% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2, PACKERS = 1) |
NV12 |
3% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2, PACKERS = 1) |
RGBA8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2, PACKERS = 1) |
ABGR8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2, PACKERS = 1) |
XBGR8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2, PACKERS = 1) |
ARGB8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2, PACKERS = 1) |
XRGB8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2, PACKERS = 1) |
RGB565 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2, PACKERS = 1) |
ABGR16161616 |
3% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2, PACKERS = 1) |
XBGR16161616 |
3% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2, PACKERS = 1) |
ARGB16161616 |
3% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2, PACKERS = 1) |
XRGB16161616 |
3% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2, PACKERS = 1) |
ABGR16161616F |
3% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2, PACKERS = 1) |
XBGR16161616F |
3% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2, PACKERS = 1) |
ARGB16161616F |
3% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2, PACKERS = 1) |
XRGB16161616F |
3% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2) |
P010 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2) |
ABGR2101010 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2) |
XBGR2101010 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2) |
ARGB2101010 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2) |
XRGB2101010 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2) |
NV12 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2) |
RGBA8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2) |
ABGR8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2) |
XBGR8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2) |
ARGB8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2) |
XRGB8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2) |
RGB565 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2) |
ABGR16161616 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2) |
XBGR16161616 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2) |
ARGB16161616 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2) |
XRGB16161616 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2) |
ABGR16161616F |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2) |
XBGR16161616F |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2) |
ARGB16161616F |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2) |
XRGB16161616F |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) |
P010 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) |
ABGR2101010 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) |
XBGR2101010 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) |
ARGB2101010 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) |
XRGB2101010 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) |
NV12 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) |
RGBA8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) |
ABGR8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) |
XBGR8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) |
ARGB8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) |
XRGB8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) |
RGB565 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) |
ABGR16161616 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) |
XBGR16161616 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) |
ARGB16161616 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) |
XRGB16161616 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) |
ABGR16161616F |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) |
XBGR16161616F |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) |
ARGB16161616F |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) |
XRGB16161616F |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, PIPE_XOR_BITS = 2) |
ABGR2101010 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, PIPE_XOR_BITS = 2) |
XBGR2101010 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, PIPE_XOR_BITS = 2) |
ARGB2101010 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, PIPE_XOR_BITS = 2) |
XRGB2101010 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, PIPE_XOR_BITS = 2) |
RGBA8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, PIPE_XOR_BITS = 2) |
ABGR8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, PIPE_XOR_BITS = 2) |
XBGR8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, PIPE_XOR_BITS = 2) |
ARGB8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, PIPE_XOR_BITS = 2) |
XRGB8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B) |
ABGR2101010 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B) |
XBGR2101010 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B) |
ARGB2101010 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B) |
XRGB2101010 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B) |
RGBA8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B) |
ABGR8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B) |
XBGR8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B) |
ARGB8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B) |
XRGB8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, PIPE_XOR_BITS = 2) |
ABGR2101010 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, PIPE_XOR_BITS = 2) |
XBGR2101010 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, PIPE_XOR_BITS = 2) |
ARGB2101010 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, PIPE_XOR_BITS = 2) |
XRGB2101010 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, PIPE_XOR_BITS = 2) |
RGBA8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, PIPE_XOR_BITS = 2) |
ABGR8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, PIPE_XOR_BITS = 2) |
XBGR8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, PIPE_XOR_BITS = 2) |
ARGB8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, PIPE_XOR_BITS = 2) |
XRGB8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B) |
ABGR2101010 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B) |
XBGR2101010 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B) |
ARGB2101010 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B) |
XRGB2101010 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B) |
RGBA8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B) |
ABGR8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B) |
XBGR8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B) |
ARGB8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B) |
XRGB8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, PIPE_XOR_BITS = 2) |
ABGR2101010 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, PIPE_XOR_BITS = 2) |
XBGR2101010 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, PIPE_XOR_BITS = 2) |
ARGB2101010 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, PIPE_XOR_BITS = 2) |
XRGB2101010 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, PIPE_XOR_BITS = 2) |
RGBA8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, PIPE_XOR_BITS = 2) |
ABGR8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, PIPE_XOR_BITS = 2) |
XBGR8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, PIPE_XOR_BITS = 2) |
ARGB8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, PIPE_XOR_BITS = 2) |
XRGB8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B) |
ABGR2101010 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B) |
XBGR2101010 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B) |
ARGB2101010 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B) |
XRGB2101010 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B) |
RGBA8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B) |
ABGR8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B) |
XBGR8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B) |
ARGB8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B) |
XRGB8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, PIPE_XOR_BITS = 2) |
ABGR2101010 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, PIPE_XOR_BITS = 2) |
XBGR2101010 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, PIPE_XOR_BITS = 2) |
ARGB2101010 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, PIPE_XOR_BITS = 2) |
XRGB2101010 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, PIPE_XOR_BITS = 2) |
RGBA8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, PIPE_XOR_BITS = 2) |
ABGR8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, PIPE_XOR_BITS = 2) |
XBGR8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, PIPE_XOR_BITS = 2) |
ARGB8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, PIPE_XOR_BITS = 2) |
XRGB8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B) |
ABGR2101010 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B) |
XBGR2101010 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B) |
ARGB2101010 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B) |
XRGB2101010 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B) |
RGBA8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B) |
ABGR8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B) |
XBGR8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B) |
ARGB8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B) |
XRGB8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, PACKERS = 1) |
ABGR2101010 |
3% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, PACKERS = 1) |
XBGR2101010 |
3% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, PACKERS = 1) |
ARGB2101010 |
3% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, PACKERS = 1) |
XRGB2101010 |
3% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, PACKERS = 1) |
RGBA8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, PACKERS = 1) |
ABGR8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, PACKERS = 1) |
XBGR8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, PACKERS = 1) |
ARGB8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, PACKERS = 1) |
XRGB8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, PACKERS = 1) |
ABGR2101010 |
3% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, PACKERS = 1) |
XBGR2101010 |
3% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, PACKERS = 1) |
ARGB2101010 |
3% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, PACKERS = 1) |
XRGB2101010 |
3% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, PACKERS = 1) |
RGBA8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, PACKERS = 1) |
ABGR8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, PACKERS = 1) |
XBGR8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, PACKERS = 1) |
ARGB8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, PACKERS = 1) |
XRGB8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, PACKERS = 1) |
ABGR2101010 |
3% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, PACKERS = 1) |
XBGR2101010 |
3% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, PACKERS = 1) |
ARGB2101010 |
3% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, PACKERS = 1) |
XRGB2101010 |
3% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, PACKERS = 1) |
RGBA8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, PACKERS = 1) |
ABGR8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, PACKERS = 1) |
XBGR8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, PACKERS = 1) |
ARGB8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, PACKERS = 1) |
XRGB8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, PACKERS = 1) |
ABGR2101010 |
3% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, PACKERS = 1) |
XBGR2101010 |
3% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, PACKERS = 1) |
ARGB2101010 |
3% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, PACKERS = 1) |
XRGB2101010 |
3% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, PACKERS = 1) |
RGBA8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, PACKERS = 1) |
ABGR8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, PACKERS = 1) |
XBGR8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, PACKERS = 1) |
ARGB8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, PACKERS = 1) |
XRGB8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 2, PACKERS = 2) |
P010 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 2, PACKERS = 2) |
ABGR2101010 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 2, PACKERS = 2) |
XBGR2101010 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 2, PACKERS = 2) |
ARGB2101010 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 2, PACKERS = 2) |
XRGB2101010 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 2, PACKERS = 2) |
NV12 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 2, PACKERS = 2) |
RGBA8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 2, PACKERS = 2) |
ABGR8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 2, PACKERS = 2) |
XBGR8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 2, PACKERS = 2) |
ARGB8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 2, PACKERS = 2) |
XRGB8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 2, PACKERS = 2) |
RGB565 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 2, PACKERS = 2) |
ABGR16161616 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 2, PACKERS = 2) |
XBGR16161616 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 2, PACKERS = 2) |
ARGB16161616 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 2, PACKERS = 2) |
XRGB16161616 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 2, PACKERS = 2) |
ABGR16161616F |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 2, PACKERS = 2) |
XBGR16161616F |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 2, PACKERS = 2) |
ARGB16161616F |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 2, PACKERS = 2) |
XRGB16161616F |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2, PACKERS = 2) |
P010 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2, PACKERS = 2) |
ABGR2101010 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2, PACKERS = 2) |
XBGR2101010 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2, PACKERS = 2) |
ARGB2101010 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2, PACKERS = 2) |
XRGB2101010 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2, PACKERS = 2) |
NV12 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2, PACKERS = 2) |
RGBA8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2, PACKERS = 2) |
ABGR8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2, PACKERS = 2) |
XBGR8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2, PACKERS = 2) |
ARGB8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2, PACKERS = 2) |
XRGB8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2, PACKERS = 2) |
RGB565 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2, PACKERS = 2) |
ABGR16161616 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2, PACKERS = 2) |
XBGR16161616 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2, PACKERS = 2) |
ARGB16161616 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2, PACKERS = 2) |
XRGB16161616 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2, PACKERS = 2) |
ABGR16161616F |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2, PACKERS = 2) |
XBGR16161616F |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2, PACKERS = 2) |
ARGB16161616F |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2, PACKERS = 2) |
XRGB16161616F |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2) |
P010 |
10% |
5% |
0% |
5% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2) |
ABGR2101010 |
10% |
5% |
0% |
5% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2) |
XBGR2101010 |
10% |
5% |
0% |
5% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2) |
ARGB2101010 |
10% |
5% |
0% |
5% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2) |
XRGB2101010 |
10% |
5% |
0% |
5% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2) |
NV12 |
10% |
5% |
0% |
5% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2) |
RGBA8888 |
10% |
5% |
0% |
5% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2) |
ABGR8888 |
10% |
5% |
0% |
5% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2) |
XBGR8888 |
10% |
5% |
0% |
5% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2) |
ARGB8888 |
10% |
5% |
0% |
5% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2) |
XRGB8888 |
10% |
5% |
0% |
5% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2) |
RGB565 |
10% |
5% |
0% |
5% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2) |
ABGR16161616 |
10% |
5% |
0% |
5% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2) |
XBGR16161616 |
10% |
5% |
0% |
5% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2) |
ARGB16161616 |
10% |
5% |
0% |
5% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2) |
XRGB16161616 |
10% |
5% |
0% |
5% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2) |
ABGR16161616F |
10% |
5% |
0% |
5% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2) |
XBGR16161616F |
10% |
5% |
0% |
5% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2) |
ARGB16161616F |
10% |
5% |
0% |
5% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2) |
XRGB16161616F |
10% |
5% |
0% |
5% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) |
P010 |
10% |
5% |
0% |
5% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) |
ABGR2101010 |
10% |
5% |
0% |
5% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) |
XBGR2101010 |
10% |
5% |
0% |
5% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) |
ARGB2101010 |
10% |
5% |
0% |
5% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) |
XRGB2101010 |
10% |
5% |
0% |
5% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) |
NV12 |
10% |
5% |
0% |
5% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) |
RGBA8888 |
10% |
5% |
0% |
5% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) |
ABGR8888 |
10% |
5% |
0% |
5% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) |
XBGR8888 |
10% |
5% |
0% |
5% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) |
ARGB8888 |
10% |
5% |
0% |
5% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) |
XRGB8888 |
10% |
5% |
0% |
5% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) |
RGB565 |
10% |
5% |
0% |
5% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) |
ABGR16161616 |
10% |
5% |
0% |
5% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) |
XBGR16161616 |
10% |
5% |
0% |
5% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) |
ARGB16161616 |
10% |
5% |
0% |
5% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) |
XRGB16161616 |
10% |
5% |
0% |
5% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) |
ABGR16161616F |
10% |
5% |
0% |
5% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) |
XBGR16161616F |
10% |
5% |
0% |
5% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) |
ARGB16161616F |
10% |
5% |
0% |
5% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) |
XRGB16161616F |
10% |
5% |
0% |
5% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, PIPE_XOR_BITS = 2) |
ABGR2101010 |
10% |
5% |
0% |
5% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, PIPE_XOR_BITS = 2) |
XBGR2101010 |
10% |
5% |
0% |
5% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, PIPE_XOR_BITS = 2) |
ARGB2101010 |
10% |
5% |
0% |
5% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, PIPE_XOR_BITS = 2) |
XRGB2101010 |
10% |
5% |
0% |
5% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, PIPE_XOR_BITS = 2) |
RGBA8888 |
10% |
5% |
0% |
5% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, PIPE_XOR_BITS = 2) |
ABGR8888 |
10% |
5% |
0% |
5% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, PIPE_XOR_BITS = 2) |
XBGR8888 |
10% |
5% |
0% |
5% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, PIPE_XOR_BITS = 2) |
ARGB8888 |
10% |
5% |
0% |
5% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, PIPE_XOR_BITS = 2) |
XRGB8888 |
10% |
5% |
0% |
5% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B) |
ABGR2101010 |
10% |
5% |
0% |
5% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B) |
XBGR2101010 |
10% |
5% |
0% |
5% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B) |
ARGB2101010 |
10% |
5% |
0% |
5% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B) |
XRGB2101010 |
10% |
5% |
0% |
5% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B) |
RGBA8888 |
10% |
5% |
0% |
5% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B) |
ABGR8888 |
10% |
5% |
0% |
5% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B) |
XBGR8888 |
10% |
5% |
0% |
5% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B) |
ARGB8888 |
10% |
5% |
0% |
5% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B) |
XRGB8888 |
10% |
5% |
0% |
5% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, PIPE_XOR_BITS = 2) |
ABGR2101010 |
10% |
5% |
0% |
5% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, PIPE_XOR_BITS = 2) |
XBGR2101010 |
10% |
5% |
0% |
5% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, PIPE_XOR_BITS = 2) |
ARGB2101010 |
10% |
5% |
0% |
5% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, PIPE_XOR_BITS = 2) |
XRGB2101010 |
10% |
5% |
0% |
5% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, PIPE_XOR_BITS = 2) |
RGBA8888 |
10% |
5% |
0% |
5% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, PIPE_XOR_BITS = 2) |
ABGR8888 |
10% |
5% |
0% |
5% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, PIPE_XOR_BITS = 2) |
XBGR8888 |
10% |
5% |
0% |
5% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, PIPE_XOR_BITS = 2) |
ARGB8888 |
10% |
5% |
0% |
5% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, PIPE_XOR_BITS = 2) |
XRGB8888 |
10% |
5% |
0% |
5% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B) |
ABGR2101010 |
10% |
5% |
0% |
5% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B) |
XBGR2101010 |
10% |
5% |
0% |
5% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B) |
ARGB2101010 |
10% |
5% |
0% |
5% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B) |
XRGB2101010 |
10% |
5% |
0% |
5% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B) |
RGBA8888 |
10% |
5% |
0% |
5% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B) |
ABGR8888 |
10% |
5% |
0% |
5% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B) |
XBGR8888 |
10% |
5% |
0% |
5% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B) |
ARGB8888 |
10% |
5% |
0% |
5% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B) |
XRGB8888 |
10% |
5% |
0% |
5% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, PIPE_XOR_BITS = 2) |
ABGR2101010 |
10% |
5% |
0% |
5% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, PIPE_XOR_BITS = 2) |
XBGR2101010 |
10% |
5% |
0% |
5% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, PIPE_XOR_BITS = 2) |
ARGB2101010 |
10% |
5% |
0% |
5% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, PIPE_XOR_BITS = 2) |
XRGB2101010 |
10% |
5% |
0% |
5% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, PIPE_XOR_BITS = 2) |
RGBA8888 |
10% |
5% |
0% |
5% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, PIPE_XOR_BITS = 2) |
ABGR8888 |
10% |
5% |
0% |
5% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, PIPE_XOR_BITS = 2) |
XBGR8888 |
10% |
5% |
0% |
5% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, PIPE_XOR_BITS = 2) |
ARGB8888 |
10% |
5% |
0% |
5% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, PIPE_XOR_BITS = 2) |
XRGB8888 |
10% |
5% |
0% |
5% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B) |
ABGR2101010 |
10% |
5% |
0% |
5% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B) |
XBGR2101010 |
10% |
5% |
0% |
5% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B) |
ARGB2101010 |
10% |
5% |
0% |
5% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B) |
XRGB2101010 |
10% |
5% |
0% |
5% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B) |
RGBA8888 |
10% |
5% |
0% |
5% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B) |
ABGR8888 |
10% |
5% |
0% |
5% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B) |
XBGR8888 |
10% |
5% |
0% |
5% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B) |
ARGB8888 |
10% |
5% |
0% |
5% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B) |
XRGB8888 |
10% |
5% |
0% |
5% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, PIPE_XOR_BITS = 2) |
ABGR2101010 |
10% |
5% |
0% |
5% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, PIPE_XOR_BITS = 2) |
XBGR2101010 |
10% |
5% |
0% |
5% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, PIPE_XOR_BITS = 2) |
ARGB2101010 |
10% |
5% |
0% |
5% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, PIPE_XOR_BITS = 2) |
XRGB2101010 |
10% |
5% |
0% |
5% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, PIPE_XOR_BITS = 2) |
RGBA8888 |
10% |
5% |
0% |
5% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, PIPE_XOR_BITS = 2) |
ABGR8888 |
10% |
5% |
0% |
5% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, PIPE_XOR_BITS = 2) |
XBGR8888 |
10% |
5% |
0% |
5% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, PIPE_XOR_BITS = 2) |
ARGB8888 |
10% |
5% |
0% |
5% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, PIPE_XOR_BITS = 2) |
XRGB8888 |
10% |
5% |
0% |
5% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B) |
ABGR2101010 |
10% |
5% |
0% |
5% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B) |
XBGR2101010 |
10% |
5% |
0% |
5% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B) |
ARGB2101010 |
10% |
5% |
0% |
5% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B) |
XRGB2101010 |
10% |
5% |
0% |
5% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B) |
RGBA8888 |
10% |
5% |
0% |
5% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B) |
ABGR8888 |
10% |
5% |
0% |
5% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B) |
XBGR8888 |
10% |
5% |
0% |
5% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B) |
ARGB8888 |
10% |
5% |
0% |
5% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B) |
XRGB8888 |
10% |
5% |
0% |
5% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, PACKERS = 2) |
ABGR2101010 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, PACKERS = 2) |
XBGR2101010 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, PACKERS = 2) |
ARGB2101010 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, PACKERS = 2) |
XRGB2101010 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, PACKERS = 2) |
RGBA8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, PACKERS = 2) |
ABGR8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, PACKERS = 2) |
XBGR8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, PACKERS = 2) |
ARGB8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, PACKERS = 2) |
XRGB8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, PACKERS = 2) |
ABGR2101010 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, PACKERS = 2) |
XBGR2101010 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, PACKERS = 2) |
ARGB2101010 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, PACKERS = 2) |
XRGB2101010 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, PACKERS = 2) |
RGBA8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, PACKERS = 2) |
ABGR8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, PACKERS = 2) |
XBGR8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, PACKERS = 2) |
ARGB8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, PACKERS = 2) |
XRGB8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, PACKERS = 2) |
ABGR2101010 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, PACKERS = 2) |
XBGR2101010 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, PACKERS = 2) |
ARGB2101010 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, PACKERS = 2) |
XRGB2101010 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, PACKERS = 2) |
RGBA8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, PACKERS = 2) |
ABGR8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, PACKERS = 2) |
XBGR8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, PACKERS = 2) |
ARGB8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, PACKERS = 2) |
XRGB8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, PACKERS = 2) |
ABGR2101010 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, PACKERS = 2) |
XBGR2101010 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, PACKERS = 2) |
ARGB2101010 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, PACKERS = 2) |
XRGB2101010 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, PACKERS = 2) |
RGBA8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, PACKERS = 2) |
ABGR8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, PACKERS = 2) |
XBGR8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, PACKERS = 2) |
ARGB8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, PACKERS = 2) |
XRGB8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 3, PACKERS = 3) |
P010 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 3, PACKERS = 3) |
ABGR2101010 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 3, PACKERS = 3) |
XBGR2101010 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 3, PACKERS = 3) |
ARGB2101010 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 3, PACKERS = 3) |
XRGB2101010 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 3, PACKERS = 3) |
NV12 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 3, PACKERS = 3) |
RGBA8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 3, PACKERS = 3) |
ABGR8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 3, PACKERS = 3) |
XBGR8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 3, PACKERS = 3) |
ARGB8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 3, PACKERS = 3) |
XRGB8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 3, PACKERS = 3) |
RGB565 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 3, PACKERS = 3) |
ABGR16161616 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 3, PACKERS = 3) |
XBGR16161616 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 3, PACKERS = 3) |
ARGB16161616 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 3, PACKERS = 3) |
XRGB16161616 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 3, PACKERS = 3) |
ABGR16161616F |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 3, PACKERS = 3) |
XBGR16161616F |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 3, PACKERS = 3) |
ARGB16161616F |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 3, PACKERS = 3) |
XRGB16161616F |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 3, PACKERS = 3) |
P010 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 3, PACKERS = 3) |
ABGR2101010 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 3, PACKERS = 3) |
XBGR2101010 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 3, PACKERS = 3) |
ARGB2101010 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 3, PACKERS = 3) |
XRGB2101010 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 3, PACKERS = 3) |
NV12 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 3, PACKERS = 3) |
RGBA8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 3, PACKERS = 3) |
ABGR8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 3, PACKERS = 3) |
XBGR8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 3, PACKERS = 3) |
ARGB8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 3, PACKERS = 3) |
XRGB8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 3, PACKERS = 3) |
RGB565 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 3, PACKERS = 3) |
ABGR16161616 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 3, PACKERS = 3) |
XBGR16161616 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 3, PACKERS = 3) |
ARGB16161616 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 3, PACKERS = 3) |
XRGB16161616 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 3, PACKERS = 3) |
ABGR16161616F |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 3, PACKERS = 3) |
XBGR16161616F |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 3, PACKERS = 3) |
ARGB16161616F |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 3, PACKERS = 3) |
XRGB16161616F |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 3) |
P010 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 3) |
ABGR2101010 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 3) |
XBGR2101010 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 3) |
ARGB2101010 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 3) |
XRGB2101010 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 3) |
NV12 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 3) |
RGBA8888 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 3) |
ABGR8888 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 3) |
XBGR8888 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 3) |
ARGB8888 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 3) |
XRGB8888 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 3) |
RGB565 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 3) |
ABGR16161616 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 3) |
XBGR16161616 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 3) |
ARGB16161616 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 3) |
XRGB16161616 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 3) |
ABGR16161616F |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 3) |
XBGR16161616F |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 3) |
ARGB16161616F |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 3) |
XRGB16161616F |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) |
P010 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) |
ABGR2101010 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) |
XBGR2101010 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) |
ARGB2101010 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) |
XRGB2101010 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) |
NV12 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) |
RGBA8888 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) |
ABGR8888 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) |
XBGR8888 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) |
ARGB8888 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) |
XRGB8888 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) |
RGB565 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) |
ABGR16161616 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) |
XBGR16161616 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) |
ARGB16161616 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) |
XRGB16161616 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) |
ABGR16161616F |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) |
XBGR16161616F |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) |
ARGB16161616F |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) |
XRGB16161616F |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, PIPE_XOR_BITS = 3) |
ABGR2101010 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, PIPE_XOR_BITS = 3) |
XBGR2101010 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, PIPE_XOR_BITS = 3) |
ARGB2101010 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, PIPE_XOR_BITS = 3) |
XRGB2101010 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, PIPE_XOR_BITS = 3) |
RGBA8888 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, PIPE_XOR_BITS = 3) |
ABGR8888 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, PIPE_XOR_BITS = 3) |
XBGR8888 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, PIPE_XOR_BITS = 3) |
ARGB8888 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, PIPE_XOR_BITS = 3) |
XRGB8888 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B) |
ABGR2101010 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B) |
XBGR2101010 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B) |
ARGB2101010 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B) |
XRGB2101010 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B) |
RGBA8888 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B) |
ABGR8888 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B) |
XBGR8888 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B) |
ARGB8888 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B) |
XRGB8888 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, PIPE_XOR_BITS = 3) |
ABGR2101010 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, PIPE_XOR_BITS = 3) |
XBGR2101010 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, PIPE_XOR_BITS = 3) |
ARGB2101010 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, PIPE_XOR_BITS = 3) |
XRGB2101010 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, PIPE_XOR_BITS = 3) |
RGBA8888 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, PIPE_XOR_BITS = 3) |
ABGR8888 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, PIPE_XOR_BITS = 3) |
XBGR8888 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, PIPE_XOR_BITS = 3) |
ARGB8888 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, PIPE_XOR_BITS = 3) |
XRGB8888 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B) |
ABGR2101010 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B) |
XBGR2101010 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B) |
ARGB2101010 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B) |
XRGB2101010 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B) |
RGBA8888 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B) |
ABGR8888 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B) |
XBGR8888 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B) |
ARGB8888 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B) |
XRGB8888 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, PIPE_XOR_BITS = 3) |
ABGR2101010 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, PIPE_XOR_BITS = 3) |
XBGR2101010 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, PIPE_XOR_BITS = 3) |
ARGB2101010 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, PIPE_XOR_BITS = 3) |
XRGB2101010 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, PIPE_XOR_BITS = 3) |
RGBA8888 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, PIPE_XOR_BITS = 3) |
ABGR8888 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, PIPE_XOR_BITS = 3) |
XBGR8888 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, PIPE_XOR_BITS = 3) |
ARGB8888 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, PIPE_XOR_BITS = 3) |
XRGB8888 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B) |
ABGR2101010 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B) |
XBGR2101010 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B) |
ARGB2101010 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B) |
XRGB2101010 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B) |
RGBA8888 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B) |
ABGR8888 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B) |
XBGR8888 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B) |
ARGB8888 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B) |
XRGB8888 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, PIPE_XOR_BITS = 3) |
ABGR2101010 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, PIPE_XOR_BITS = 3) |
XBGR2101010 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, PIPE_XOR_BITS = 3) |
ARGB2101010 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, PIPE_XOR_BITS = 3) |
XRGB2101010 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, PIPE_XOR_BITS = 3) |
RGBA8888 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, PIPE_XOR_BITS = 3) |
ABGR8888 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, PIPE_XOR_BITS = 3) |
XBGR8888 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, PIPE_XOR_BITS = 3) |
ARGB8888 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, PIPE_XOR_BITS = 3) |
XRGB8888 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B) |
ABGR2101010 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B) |
XBGR2101010 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B) |
ARGB2101010 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B) |
XRGB2101010 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B) |
RGBA8888 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B) |
ABGR8888 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B) |
XBGR8888 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B) |
ARGB8888 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B) |
XRGB8888 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 3, PACKERS = 3) |
ABGR2101010 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 3, PACKERS = 3) |
XBGR2101010 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 3, PACKERS = 3) |
ARGB2101010 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 3, PACKERS = 3) |
XRGB2101010 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 3, PACKERS = 3) |
RGBA8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 3, PACKERS = 3) |
ABGR8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 3, PACKERS = 3) |
XBGR8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 3, PACKERS = 3) |
ARGB8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 3, PACKERS = 3) |
XRGB8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 3, PACKERS = 3) |
ABGR2101010 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 3, PACKERS = 3) |
XBGR2101010 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 3, PACKERS = 3) |
ARGB2101010 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 3, PACKERS = 3) |
XRGB2101010 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 3, PACKERS = 3) |
RGBA8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 3, PACKERS = 3) |
ABGR8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 3, PACKERS = 3) |
XBGR8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 3, PACKERS = 3) |
ARGB8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 3, PACKERS = 3) |
XRGB8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 3, PACKERS = 3) |
ABGR2101010 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 3, PACKERS = 3) |
XBGR2101010 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 3, PACKERS = 3) |
ARGB2101010 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 3, PACKERS = 3) |
XRGB2101010 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 3, PACKERS = 3) |
RGBA8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 3, PACKERS = 3) |
ABGR8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 3, PACKERS = 3) |
XBGR8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 3, PACKERS = 3) |
ARGB8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 3, PACKERS = 3) |
XRGB8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 3, PACKERS = 3) |
ABGR2101010 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 3, PACKERS = 3) |
XBGR2101010 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 3, PACKERS = 3) |
ARGB2101010 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 3, PACKERS = 3) |
XRGB2101010 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 3, PACKERS = 3) |
RGBA8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 3, PACKERS = 3) |
ABGR8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 3, PACKERS = 3) |
XBGR8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 3, PACKERS = 3) |
ARGB8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 3, PACKERS = 3) |
XRGB8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 4, PACKERS = 3) |
P010 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 4, PACKERS = 3) |
ABGR2101010 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 4, PACKERS = 3) |
XBGR2101010 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 4, PACKERS = 3) |
ARGB2101010 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 4, PACKERS = 3) |
XRGB2101010 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 4, PACKERS = 3) |
NV12 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 4, PACKERS = 3) |
RGBA8888 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 4, PACKERS = 3) |
ABGR8888 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 4, PACKERS = 3) |
XBGR8888 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 4, PACKERS = 3) |
ARGB8888 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 4, PACKERS = 3) |
XRGB8888 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 4, PACKERS = 3) |
RGB565 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 4, PACKERS = 3) |
ABGR16161616 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 4, PACKERS = 3) |
XBGR16161616 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 4, PACKERS = 3) |
ARGB16161616 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 4, PACKERS = 3) |
XRGB16161616 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 4, PACKERS = 3) |
ABGR16161616F |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 4, PACKERS = 3) |
XBGR16161616F |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 4, PACKERS = 3) |
ARGB16161616F |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 4, PACKERS = 3) |
XRGB16161616F |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4, PACKERS = 3) |
P010 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4, PACKERS = 3) |
ABGR2101010 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4, PACKERS = 3) |
XBGR2101010 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4, PACKERS = 3) |
ARGB2101010 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4, PACKERS = 3) |
XRGB2101010 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4, PACKERS = 3) |
NV12 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4, PACKERS = 3) |
RGBA8888 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4, PACKERS = 3) |
ABGR8888 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4, PACKERS = 3) |
XBGR8888 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4, PACKERS = 3) |
ARGB8888 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4, PACKERS = 3) |
XRGB8888 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4, PACKERS = 3) |
RGB565 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4, PACKERS = 3) |
ABGR16161616 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4, PACKERS = 3) |
XBGR16161616 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4, PACKERS = 3) |
ARGB16161616 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4, PACKERS = 3) |
XRGB16161616 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4, PACKERS = 3) |
ABGR16161616F |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4, PACKERS = 3) |
XBGR16161616F |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4, PACKERS = 3) |
ARGB16161616F |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4, PACKERS = 3) |
XRGB16161616F |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 4, PACKERS = 3) |
ABGR2101010 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 4, PACKERS = 3) |
XBGR2101010 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 4, PACKERS = 3) |
ARGB2101010 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 4, PACKERS = 3) |
XRGB2101010 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 4, PACKERS = 3) |
RGBA8888 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 4, PACKERS = 3) |
ABGR8888 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 4, PACKERS = 3) |
XBGR8888 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 4, PACKERS = 3) |
ARGB8888 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 4, PACKERS = 3) |
XRGB8888 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 4, PACKERS = 3) |
ABGR2101010 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 4, PACKERS = 3) |
XBGR2101010 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 4, PACKERS = 3) |
ARGB2101010 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 4, PACKERS = 3) |
XRGB2101010 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 4, PACKERS = 3) |
RGBA8888 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 4, PACKERS = 3) |
ABGR8888 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 4, PACKERS = 3) |
XBGR8888 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 4, PACKERS = 3) |
ARGB8888 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 4, PACKERS = 3) |
XRGB8888 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 4, PACKERS = 3) |
ABGR2101010 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 4, PACKERS = 3) |
XBGR2101010 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 4, PACKERS = 3) |
ARGB2101010 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 4, PACKERS = 3) |
XRGB2101010 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 4, PACKERS = 3) |
RGBA8888 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 4, PACKERS = 3) |
ABGR8888 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 4, PACKERS = 3) |
XBGR8888 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 4, PACKERS = 3) |
ARGB8888 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 4, PACKERS = 3) |
XRGB8888 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 4, PACKERS = 3) |
ABGR2101010 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 4, PACKERS = 3) |
XBGR2101010 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 4, PACKERS = 3) |
ARGB2101010 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 4, PACKERS = 3) |
XRGB2101010 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 4, PACKERS = 3) |
RGBA8888 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 4, PACKERS = 3) |
ABGR8888 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 4, PACKERS = 3) |
XBGR8888 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 4, PACKERS = 3) |
ARGB8888 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 4, PACKERS = 3) |
XRGB8888 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 4, PACKERS = 4) |
P010 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 4, PACKERS = 4) |
ABGR2101010 |
3% |
5% |
0% |
5% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 4, PACKERS = 4) |
XBGR2101010 |
3% |
5% |
0% |
5% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 4, PACKERS = 4) |
ARGB2101010 |
3% |
5% |
0% |
5% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 4, PACKERS = 4) |
XRGB2101010 |
3% |
5% |
0% |
5% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 4, PACKERS = 4) |
NV21 |
3% |
0% |
0% |
2% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 4, PACKERS = 4) |
NV12 |
6% |
5% |
0% |
5% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 4, PACKERS = 4) |
RGBA8888 |
10% |
5% |
0% |
5% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 4, PACKERS = 4) |
ABGR8888 |
10% |
5% |
0% |
5% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 4, PACKERS = 4) |
XBGR8888 |
10% |
5% |
0% |
5% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 4, PACKERS = 4) |
ARGB8888 |
10% |
5% |
0% |
5% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 4, PACKERS = 4) |
XRGB8888 |
10% |
5% |
0% |
5% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 4, PACKERS = 4) |
RGB565 |
10% |
5% |
0% |
5% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 4, PACKERS = 4) |
ABGR16161616 |
3% |
5% |
0% |
5% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 4, PACKERS = 4) |
XBGR16161616 |
3% |
5% |
0% |
5% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 4, PACKERS = 4) |
ARGB16161616 |
3% |
5% |
0% |
5% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 4, PACKERS = 4) |
XRGB16161616 |
3% |
5% |
0% |
5% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 4, PACKERS = 4) |
ABGR16161616F |
3% |
5% |
0% |
5% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 4, PACKERS = 4) |
XBGR16161616F |
3% |
5% |
0% |
5% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 4, PACKERS = 4) |
ARGB16161616F |
3% |
5% |
0% |
5% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 4, PACKERS = 4) |
XRGB16161616F |
3% |
5% |
0% |
5% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4, PACKERS = 4) |
P010 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4, PACKERS = 4) |
ABGR2101010 |
3% |
5% |
0% |
5% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4, PACKERS = 4) |
XBGR2101010 |
3% |
5% |
0% |
5% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4, PACKERS = 4) |
ARGB2101010 |
3% |
5% |
0% |
5% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4, PACKERS = 4) |
XRGB2101010 |
3% |
5% |
0% |
5% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4, PACKERS = 4) |
NV21 |
3% |
0% |
0% |
2% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4, PACKERS = 4) |
NV12 |
6% |
5% |
0% |
5% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4, PACKERS = 4) |
RGBA8888 |
10% |
5% |
0% |
5% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4, PACKERS = 4) |
ABGR8888 |
10% |
5% |
0% |
5% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4, PACKERS = 4) |
XBGR8888 |
10% |
5% |
0% |
5% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4, PACKERS = 4) |
ARGB8888 |
10% |
5% |
0% |
5% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4, PACKERS = 4) |
XRGB8888 |
10% |
5% |
0% |
5% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4, PACKERS = 4) |
RGB565 |
10% |
5% |
0% |
5% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4, PACKERS = 4) |
ABGR16161616 |
3% |
5% |
0% |
5% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4, PACKERS = 4) |
XBGR16161616 |
3% |
5% |
0% |
5% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4, PACKERS = 4) |
ARGB16161616 |
3% |
5% |
0% |
5% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4, PACKERS = 4) |
XRGB16161616 |
3% |
5% |
0% |
5% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4, PACKERS = 4) |
ABGR16161616F |
3% |
5% |
0% |
5% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4, PACKERS = 4) |
XBGR16161616F |
3% |
5% |
0% |
5% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4, PACKERS = 4) |
ARGB16161616F |
3% |
5% |
0% |
5% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4, PACKERS = 4) |
XRGB16161616F |
3% |
5% |
0% |
5% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4) |
P010 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4) |
ABGR2101010 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4) |
XBGR2101010 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4) |
ARGB2101010 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4) |
XRGB2101010 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4) |
NV12 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4) |
RGBA8888 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4) |
ABGR8888 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4) |
XBGR8888 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4) |
ARGB8888 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4) |
XRGB8888 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4) |
RGB565 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4) |
ABGR16161616 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4) |
XBGR16161616 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4) |
ARGB16161616 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4) |
XRGB16161616 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4) |
ABGR16161616F |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4) |
XBGR16161616F |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4) |
ARGB16161616F |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4) |
XRGB16161616F |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) |
P010 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) |
ABGR2101010 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) |
XBGR2101010 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) |
ARGB2101010 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) |
XRGB2101010 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) |
NV12 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) |
RGBA8888 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) |
ABGR8888 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) |
XBGR8888 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) |
ARGB8888 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) |
XRGB8888 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) |
RGB565 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) |
ABGR16161616 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) |
XBGR16161616 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) |
ARGB16161616 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) |
XRGB16161616 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) |
ABGR16161616F |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) |
XBGR16161616F |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) |
ARGB16161616F |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) |
XRGB16161616F |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, PIPE_XOR_BITS = 4) |
ABGR2101010 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, PIPE_XOR_BITS = 4) |
XBGR2101010 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, PIPE_XOR_BITS = 4) |
ARGB2101010 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, PIPE_XOR_BITS = 4) |
XRGB2101010 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, PIPE_XOR_BITS = 4) |
RGBA8888 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, PIPE_XOR_BITS = 4) |
ABGR8888 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, PIPE_XOR_BITS = 4) |
XBGR8888 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, PIPE_XOR_BITS = 4) |
ARGB8888 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, PIPE_XOR_BITS = 4) |
XRGB8888 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B) |
ABGR2101010 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B) |
XBGR2101010 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B) |
ARGB2101010 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B) |
XRGB2101010 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B) |
RGBA8888 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B) |
ABGR8888 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B) |
XBGR8888 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B) |
ARGB8888 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B) |
XRGB8888 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, PIPE_XOR_BITS = 4) |
ABGR2101010 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, PIPE_XOR_BITS = 4) |
XBGR2101010 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, PIPE_XOR_BITS = 4) |
ARGB2101010 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, PIPE_XOR_BITS = 4) |
XRGB2101010 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, PIPE_XOR_BITS = 4) |
RGBA8888 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, PIPE_XOR_BITS = 4) |
ABGR8888 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, PIPE_XOR_BITS = 4) |
XBGR8888 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, PIPE_XOR_BITS = 4) |
ARGB8888 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, PIPE_XOR_BITS = 4) |
XRGB8888 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B) |
ABGR2101010 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B) |
XBGR2101010 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B) |
ARGB2101010 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B) |
XRGB2101010 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B) |
RGBA8888 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B) |
ABGR8888 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B) |
XBGR8888 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B) |
ARGB8888 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B) |
XRGB8888 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, PIPE_XOR_BITS = 4) |
ABGR2101010 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, PIPE_XOR_BITS = 4) |
XBGR2101010 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, PIPE_XOR_BITS = 4) |
ARGB2101010 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, PIPE_XOR_BITS = 4) |
XRGB2101010 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, PIPE_XOR_BITS = 4) |
RGBA8888 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, PIPE_XOR_BITS = 4) |
ABGR8888 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, PIPE_XOR_BITS = 4) |
XBGR8888 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, PIPE_XOR_BITS = 4) |
ARGB8888 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, PIPE_XOR_BITS = 4) |
XRGB8888 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B) |
ABGR2101010 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B) |
XBGR2101010 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B) |
ARGB2101010 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B) |
XRGB2101010 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B) |
RGBA8888 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B) |
ABGR8888 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B) |
XBGR8888 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B) |
ARGB8888 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B) |
XRGB8888 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, PIPE_XOR_BITS = 4) |
ABGR2101010 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, PIPE_XOR_BITS = 4) |
XBGR2101010 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, PIPE_XOR_BITS = 4) |
ARGB2101010 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, PIPE_XOR_BITS = 4) |
XRGB2101010 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, PIPE_XOR_BITS = 4) |
RGBA8888 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, PIPE_XOR_BITS = 4) |
ABGR8888 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, PIPE_XOR_BITS = 4) |
XBGR8888 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, PIPE_XOR_BITS = 4) |
ARGB8888 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, PIPE_XOR_BITS = 4) |
XRGB8888 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B) |
ABGR2101010 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B) |
XBGR2101010 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B) |
ARGB2101010 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B) |
XRGB2101010 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B) |
RGBA8888 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B) |
ABGR8888 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B) |
XBGR8888 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B) |
ARGB8888 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B) |
XRGB8888 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 4, PACKERS = 4) |
ABGR2101010 |
3% |
5% |
0% |
5% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 4, PACKERS = 4) |
XBGR2101010 |
3% |
5% |
0% |
5% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 4, PACKERS = 4) |
ARGB2101010 |
3% |
5% |
0% |
5% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 4, PACKERS = 4) |
XRGB2101010 |
3% |
5% |
0% |
5% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 4, PACKERS = 4) |
RGBA8888 |
10% |
5% |
0% |
5% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 4, PACKERS = 4) |
ABGR8888 |
10% |
5% |
0% |
5% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 4, PACKERS = 4) |
XBGR8888 |
10% |
5% |
0% |
5% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 4, PACKERS = 4) |
ARGB8888 |
10% |
5% |
0% |
5% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 4, PACKERS = 4) |
XRGB8888 |
10% |
5% |
0% |
5% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 4, PACKERS = 4) |
ABGR2101010 |
3% |
5% |
0% |
5% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 4, PACKERS = 4) |
XBGR2101010 |
3% |
5% |
0% |
5% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 4, PACKERS = 4) |
ARGB2101010 |
3% |
5% |
0% |
5% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 4, PACKERS = 4) |
XRGB2101010 |
3% |
5% |
0% |
5% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 4, PACKERS = 4) |
RGBA8888 |
10% |
5% |
0% |
5% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 4, PACKERS = 4) |
ABGR8888 |
10% |
5% |
0% |
5% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 4, PACKERS = 4) |
XBGR8888 |
10% |
5% |
0% |
5% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 4, PACKERS = 4) |
ARGB8888 |
10% |
5% |
0% |
5% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 4, PACKERS = 4) |
XRGB8888 |
10% |
5% |
0% |
5% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 4, PACKERS = 4) |
ABGR2101010 |
3% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 4, PACKERS = 4) |
XBGR2101010 |
3% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 4, PACKERS = 4) |
ARGB2101010 |
3% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 4, PACKERS = 4) |
XRGB2101010 |
3% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 4, PACKERS = 4) |
RGBA8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 4, PACKERS = 4) |
ABGR8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 4, PACKERS = 4) |
XBGR8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 4, PACKERS = 4) |
ARGB8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 4, PACKERS = 4) |
XRGB8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 4, PACKERS = 4) |
ABGR2101010 |
3% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 4, PACKERS = 4) |
XBGR2101010 |
3% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 4, PACKERS = 4) |
ARGB2101010 |
3% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 4, PACKERS = 4) |
XRGB2101010 |
3% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 4, PACKERS = 4) |
RGBA8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 4, PACKERS = 4) |
ABGR8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 4, PACKERS = 4) |
XBGR8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 4, PACKERS = 4) |
ARGB8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 4, PACKERS = 4) |
XRGB8888 |
6% |
4% |
0% |
4% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 5) |
P010 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 5) |
ABGR2101010 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 5) |
XBGR2101010 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 5) |
ARGB2101010 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 5) |
XRGB2101010 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 5) |
NV12 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 5) |
RGBA8888 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 5) |
ABGR8888 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 5) |
XBGR8888 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 5) |
ARGB8888 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 5) |
XRGB8888 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 5) |
RGB565 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 5) |
ABGR16161616 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 5) |
XBGR16161616 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 5) |
ARGB16161616 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 5) |
XRGB16161616 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 5) |
ABGR16161616F |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 5) |
XBGR16161616F |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 5) |
ARGB16161616F |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 5) |
XRGB16161616F |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) |
P010 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) |
ABGR2101010 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) |
XBGR2101010 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) |
ARGB2101010 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) |
XRGB2101010 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) |
NV12 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) |
RGBA8888 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) |
ABGR8888 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) |
XBGR8888 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) |
ARGB8888 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) |
XRGB8888 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) |
RGB565 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) |
ABGR16161616 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) |
XBGR16161616 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) |
ARGB16161616 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) |
XRGB16161616 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) |
ABGR16161616F |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) |
XBGR16161616F |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) |
ARGB16161616F |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) |
XRGB16161616F |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, PIPE_XOR_BITS = 5) |
ABGR2101010 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, PIPE_XOR_BITS = 5) |
XBGR2101010 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, PIPE_XOR_BITS = 5) |
ARGB2101010 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, PIPE_XOR_BITS = 5) |
XRGB2101010 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, PIPE_XOR_BITS = 5) |
RGBA8888 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, PIPE_XOR_BITS = 5) |
ABGR8888 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, PIPE_XOR_BITS = 5) |
XBGR8888 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, PIPE_XOR_BITS = 5) |
ARGB8888 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, PIPE_XOR_BITS = 5) |
XRGB8888 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B) |
ABGR2101010 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B) |
XBGR2101010 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B) |
ARGB2101010 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B) |
XRGB2101010 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B) |
RGBA8888 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B) |
ABGR8888 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B) |
XBGR8888 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B) |
ARGB8888 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B) |
XRGB8888 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, PIPE_XOR_BITS = 5) |
ABGR2101010 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, PIPE_XOR_BITS = 5) |
XBGR2101010 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, PIPE_XOR_BITS = 5) |
ARGB2101010 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, PIPE_XOR_BITS = 5) |
XRGB2101010 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, PIPE_XOR_BITS = 5) |
RGBA8888 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, PIPE_XOR_BITS = 5) |
ABGR8888 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, PIPE_XOR_BITS = 5) |
XBGR8888 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, PIPE_XOR_BITS = 5) |
ARGB8888 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, PIPE_XOR_BITS = 5) |
XRGB8888 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B) |
ABGR2101010 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B) |
XBGR2101010 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B) |
ARGB2101010 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B) |
XRGB2101010 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B) |
RGBA8888 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B) |
ABGR8888 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B) |
XBGR8888 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B) |
ARGB8888 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B) |
XRGB8888 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, PIPE_XOR_BITS = 5) |
ABGR2101010 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, PIPE_XOR_BITS = 5) |
XBGR2101010 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, PIPE_XOR_BITS = 5) |
ARGB2101010 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, PIPE_XOR_BITS = 5) |
XRGB2101010 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, PIPE_XOR_BITS = 5) |
RGBA8888 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, PIPE_XOR_BITS = 5) |
ABGR8888 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, PIPE_XOR_BITS = 5) |
XBGR8888 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, PIPE_XOR_BITS = 5) |
ARGB8888 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, PIPE_XOR_BITS = 5) |
XRGB8888 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B) |
ABGR2101010 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B) |
XBGR2101010 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B) |
ARGB2101010 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B) |
XRGB2101010 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B) |
RGBA8888 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B) |
ABGR8888 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B) |
XBGR8888 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B) |
ARGB8888 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B) |
XRGB8888 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, PIPE_XOR_BITS = 5) |
ABGR2101010 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, PIPE_XOR_BITS = 5) |
XBGR2101010 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, PIPE_XOR_BITS = 5) |
ARGB2101010 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, PIPE_XOR_BITS = 5) |
XRGB2101010 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, PIPE_XOR_BITS = 5) |
RGBA8888 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, PIPE_XOR_BITS = 5) |
ABGR8888 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, PIPE_XOR_BITS = 5) |
XBGR8888 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, PIPE_XOR_BITS = 5) |
ARGB8888 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, PIPE_XOR_BITS = 5) |
XRGB8888 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B) |
ABGR2101010 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B) |
XBGR2101010 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B) |
ARGB2101010 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B) |
XRGB2101010 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B) |
RGBA8888 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B) |
ABGR8888 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B) |
XBGR8888 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B) |
ARGB8888 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B) |
XRGB8888 |
3% |
2% |
0% |
2% |
| AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_S_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_MAX_COMPRESSED_BLOCK = 64B, PIPE_XOR_BITS = 2, BANK_XOR_BITS = 0, RB = 1, PIPE = 2) |
ABGR2101010 |
19% |
11% |
0% |
11% |
| AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_S_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_MAX_COMPRESSED_BLOCK = 64B, PIPE_XOR_BITS = 2, BANK_XOR_BITS = 0, RB = 1, PIPE = 2) |
XBGR2101010 |
19% |
11% |
0% |
11% |
| AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_S_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_MAX_COMPRESSED_BLOCK = 64B, PIPE_XOR_BITS = 2, BANK_XOR_BITS = 0, RB = 1, PIPE = 2) |
ARGB2101010 |
19% |
11% |
0% |
11% |
| AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_S_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_MAX_COMPRESSED_BLOCK = 64B, PIPE_XOR_BITS = 2, BANK_XOR_BITS = 0, RB = 1, PIPE = 2) |
XRGB2101010 |
19% |
11% |
0% |
11% |
| AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_S_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_MAX_COMPRESSED_BLOCK = 64B, PIPE_XOR_BITS = 2, BANK_XOR_BITS = 0, RB = 1, PIPE = 2) |
RGBA8888 |
19% |
11% |
0% |
11% |
| AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_S_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_MAX_COMPRESSED_BLOCK = 64B, PIPE_XOR_BITS = 2, BANK_XOR_BITS = 0, RB = 1, PIPE = 2) |
ABGR8888 |
19% |
11% |
0% |
11% |
| AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_S_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_MAX_COMPRESSED_BLOCK = 64B, PIPE_XOR_BITS = 2, BANK_XOR_BITS = 0, RB = 1, PIPE = 2) |
XBGR8888 |
19% |
11% |
0% |
11% |
| AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_S_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_MAX_COMPRESSED_BLOCK = 64B, PIPE_XOR_BITS = 2, BANK_XOR_BITS = 0, RB = 1, PIPE = 2) |
ARGB8888 |
19% |
11% |
0% |
11% |
| AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_S_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_MAX_COMPRESSED_BLOCK = 64B, PIPE_XOR_BITS = 2, BANK_XOR_BITS = 0, RB = 1, PIPE = 2) |
XRGB8888 |
19% |
11% |
0% |
11% |
| AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_S_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, BANK_XOR_BITS = 0, RB = 1, PIPE = 2) |
ABGR2101010 |
13% |
7% |
0% |
7% |
| AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_S_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, BANK_XOR_BITS = 0, RB = 1, PIPE = 2) |
XBGR2101010 |
13% |
7% |
0% |
7% |
| AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_S_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, BANK_XOR_BITS = 0, RB = 1, PIPE = 2) |
ARGB2101010 |
13% |
7% |
0% |
7% |
| AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_S_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, BANK_XOR_BITS = 0, RB = 1, PIPE = 2) |
XRGB2101010 |
13% |
7% |
0% |
7% |
| AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_S_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, BANK_XOR_BITS = 0, RB = 1, PIPE = 2) |
RGBA8888 |
13% |
7% |
0% |
7% |
| AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_S_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, BANK_XOR_BITS = 0, RB = 1, PIPE = 2) |
ABGR8888 |
13% |
7% |
0% |
7% |
| AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_S_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, BANK_XOR_BITS = 0, RB = 1, PIPE = 2) |
XBGR8888 |
13% |
7% |
0% |
7% |
| AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_S_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, BANK_XOR_BITS = 0, RB = 1, PIPE = 2) |
ARGB8888 |
13% |
7% |
0% |
7% |
| AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_S_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, BANK_XOR_BITS = 0, RB = 1, PIPE = 2) |
XRGB8888 |
13% |
7% |
0% |
7% |