DRM database formats

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Filters: ABGR2101010 ×

Input formats

The percentages indicate the number of devices supporting the format and modifier. For instance, "50%" in the column for the "i915" driver would mean that half the known Intel devices support that format and modifier.

Modifier Format Planes Drivers
overlay primary cursor amdgpu i915 imx-dcss nouveau nvidia-drm rockchip starfive vc4
LINEAR ABGR2101010 100% 100% 100% 100% 100% 100% 100% 100% 100% 100% 100%
I915_X_TILED ABGR2101010 27% 16% 0% 0% 100% 0% 0% 0% 0% 0% 0%
I915_Y_TILED ABGR2101010 16% 10% 0% 0% 61% 0% 0% 0% 0% 0% 0%
I915_Yf_TILED ABGR2101010 3% 2% 0% 0% 11% 0% 0% 0% 0% 0% 0%
I915_4_TILED ABGR2101010 6% 4% 0% 0% 22% 0% 0% 0% 0% 0% 0%
AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_S) ABGR2101010 15% 16% 0% 49% 0% 0% 0% 0% 0% 0% 0%
AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_D) ABGR2101010 0% 1% 0% 3% 0% 0% 0% 0% 0% 0% 0%
AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 2, BANK_XOR_BITS = 0) ABGR2101010 4% 5% 0% 14% 0% 0% 0% 0% 0% 0% 0%
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 2, PACKERS = 0) ABGR2101010 1% 1% 0% 3% 0% 0% 0% 0% 0% 0% 0%
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2, PACKERS = 0) ABGR2101010 1% 1% 0% 3% 0% 0% 0% 0% 0% 0% 0%
AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_S_X, DCC, DCC_INDEPENDENT_64B, DCC_MAX_COMPRESSED_BLOCK = 64B, PIPE_XOR_BITS = 2, BANK_XOR_BITS = 0, RB = 0) ABGR2101010 4% 5% 0% 14% 0% 0% 0% 0% 0% 0% 0%
AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_S_X, DCC, DCC_INDEPENDENT_64B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, BANK_XOR_BITS = 0, RB = 0) ABGR2101010 3% 3% 0% 9% 0% 0% 0% 0% 0% 0% 0%
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, PACKERS = 0) ABGR2101010 1% 1% 0% 3% 0% 0% 0% 0% 0% 0% 0%
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, PACKERS = 0) ABGR2101010 1% 1% 0% 3% 0% 0% 0% 0% 0% 0% 0%
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, PACKERS = 0) ABGR2101010 1% 1% 0% 3% 0% 0% 0% 0% 0% 0% 0%
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, PACKERS = 0) ABGR2101010 1% 1% 0% 3% 0% 0% 0% 0% 0% 0% 0%
AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 3) ABGR2101010 1% 1% 0% 3% 0% 0% 0% 0% 0% 0% 0%
AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 3) ABGR2101010 1% 1% 0% 3% 0% 0% 0% 0% 0% 0% 0%
AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 3) ABGR2101010 1% 1% 0% 3% 0% 0% 0% 0% 0% 0% 0%
AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 3) ABGR2101010 1% 1% 0% 3% 0% 0% 0% 0% 0% 0% 0%
AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 4) ABGR2101010 0% 1% 0% 3% 0% 0% 0% 0% 0% 0% 0%
AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4) ABGR2101010 0% 1% 0% 3% 0% 0% 0% 0% 0% 0% 0%
AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 4) ABGR2101010 0% 1% 0% 3% 0% 0% 0% 0% 0% 0% 0%
AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 4) ABGR2101010 0% 1% 0% 3% 0% 0% 0% 0% 0% 0% 0%
AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_D_X, PIPE_XOR_BITS = 4, BANK_XOR_BITS = 4) ABGR2101010 0% 1% 0% 3% 0% 0% 0% 0% 0% 0% 0%
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 2, PACKERS = 1) ABGR2101010 1% 1% 0% 3% 0% 0% 0% 0% 0% 0% 0%
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2, PACKERS = 1) ABGR2101010 1% 1% 0% 3% 0% 0% 0% 0% 0% 0% 0%
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, PACKERS = 1) ABGR2101010 1% 1% 0% 3% 0% 0% 0% 0% 0% 0% 0%
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, PACKERS = 1) ABGR2101010 1% 1% 0% 3% 0% 0% 0% 0% 0% 0% 0%
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, PACKERS = 1) ABGR2101010 1% 1% 0% 3% 0% 0% 0% 0% 0% 0% 0%
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, PACKERS = 1) ABGR2101010 1% 1% 0% 3% 0% 0% 0% 0% 0% 0% 0%
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 2, PACKERS = 2) ABGR2101010 1% 2% 0% 6% 0% 0% 0% 0% 0% 0% 0%
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2, PACKERS = 2) ABGR2101010 1% 2% 0% 6% 0% 0% 0% 0% 0% 0% 0%
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2) ABGR2101010 1% 1% 0% 3% 0% 0% 0% 0% 0% 0% 0%
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) ABGR2101010 1% 1% 0% 3% 0% 0% 0% 0% 0% 0% 0%
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, PIPE_XOR_BITS = 2) ABGR2101010 1% 1% 0% 3% 0% 0% 0% 0% 0% 0% 0%
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B) ABGR2101010 1% 1% 0% 3% 0% 0% 0% 0% 0% 0% 0%
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, PIPE_XOR_BITS = 2) ABGR2101010 1% 1% 0% 3% 0% 0% 0% 0% 0% 0% 0%
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B) ABGR2101010 1% 1% 0% 3% 0% 0% 0% 0% 0% 0% 0%
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, PIPE_XOR_BITS = 2) ABGR2101010 1% 1% 0% 3% 0% 0% 0% 0% 0% 0% 0%
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B) ABGR2101010 1% 1% 0% 3% 0% 0% 0% 0% 0% 0% 0%
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, PIPE_XOR_BITS = 2) ABGR2101010 1% 1% 0% 3% 0% 0% 0% 0% 0% 0% 0%
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B) ABGR2101010 1% 1% 0% 3% 0% 0% 0% 0% 0% 0% 0%
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, PACKERS = 2) ABGR2101010 1% 2% 0% 6% 0% 0% 0% 0% 0% 0% 0%
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, PACKERS = 2) ABGR2101010 1% 2% 0% 6% 0% 0% 0% 0% 0% 0% 0%
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, PACKERS = 2) ABGR2101010 1% 2% 0% 6% 0% 0% 0% 0% 0% 0% 0%
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, PACKERS = 2) ABGR2101010 1% 2% 0% 6% 0% 0% 0% 0% 0% 0% 0%
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 3, PACKERS = 3) ABGR2101010 1% 2% 0% 6% 0% 0% 0% 0% 0% 0% 0%
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 3, PACKERS = 3) ABGR2101010 1% 2% 0% 6% 0% 0% 0% 0% 0% 0% 0%
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 3) ABGR2101010 0% 1% 0% 3% 0% 0% 0% 0% 0% 0% 0%
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) ABGR2101010 0% 1% 0% 3% 0% 0% 0% 0% 0% 0% 0%
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, PIPE_XOR_BITS = 3) ABGR2101010 0% 1% 0% 3% 0% 0% 0% 0% 0% 0% 0%
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B) ABGR2101010 0% 1% 0% 3% 0% 0% 0% 0% 0% 0% 0%
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, PIPE_XOR_BITS = 3) ABGR2101010 0% 1% 0% 3% 0% 0% 0% 0% 0% 0% 0%
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B) ABGR2101010 0% 1% 0% 3% 0% 0% 0% 0% 0% 0% 0%
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, PIPE_XOR_BITS = 3) ABGR2101010 0% 1% 0% 3% 0% 0% 0% 0% 0% 0% 0%
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B) ABGR2101010 0% 1% 0% 3% 0% 0% 0% 0% 0% 0% 0%
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, PIPE_XOR_BITS = 3) ABGR2101010 0% 1% 0% 3% 0% 0% 0% 0% 0% 0% 0%
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B) ABGR2101010 0% 1% 0% 3% 0% 0% 0% 0% 0% 0% 0%
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 3, PACKERS = 3) ABGR2101010 1% 2% 0% 6% 0% 0% 0% 0% 0% 0% 0%
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 3, PACKERS = 3) ABGR2101010 1% 2% 0% 6% 0% 0% 0% 0% 0% 0% 0%
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 3, PACKERS = 3) ABGR2101010 1% 2% 0% 6% 0% 0% 0% 0% 0% 0% 0%
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 3, PACKERS = 3) ABGR2101010 1% 2% 0% 6% 0% 0% 0% 0% 0% 0% 0%
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 4, PACKERS = 3) ABGR2101010 1% 1% 0% 3% 0% 0% 0% 0% 0% 0% 0%
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4, PACKERS = 3) ABGR2101010 1% 1% 0% 3% 0% 0% 0% 0% 0% 0% 0%
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 4, PACKERS = 3) ABGR2101010 1% 1% 0% 3% 0% 0% 0% 0% 0% 0% 0%
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 4, PACKERS = 3) ABGR2101010 1% 1% 0% 3% 0% 0% 0% 0% 0% 0% 0%
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 4, PACKERS = 3) ABGR2101010 1% 1% 0% 3% 0% 0% 0% 0% 0% 0% 0%
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 4, PACKERS = 3) ABGR2101010 1% 1% 0% 3% 0% 0% 0% 0% 0% 0% 0%
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 4, PACKERS = 4) ABGR2101010 1% 3% 0% 9% 0% 0% 0% 0% 0% 0% 0%
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4, PACKERS = 4) ABGR2101010 1% 3% 0% 9% 0% 0% 0% 0% 0% 0% 0%
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4) ABGR2101010 1% 1% 0% 3% 0% 0% 0% 0% 0% 0% 0%
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) ABGR2101010 1% 1% 0% 3% 0% 0% 0% 0% 0% 0% 0%
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, PIPE_XOR_BITS = 4) ABGR2101010 1% 1% 0% 3% 0% 0% 0% 0% 0% 0% 0%
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B) ABGR2101010 1% 1% 0% 3% 0% 0% 0% 0% 0% 0% 0%
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, PIPE_XOR_BITS = 4) ABGR2101010 1% 1% 0% 3% 0% 0% 0% 0% 0% 0% 0%
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B) ABGR2101010 1% 1% 0% 3% 0% 0% 0% 0% 0% 0% 0%
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, PIPE_XOR_BITS = 4) ABGR2101010 1% 1% 0% 3% 0% 0% 0% 0% 0% 0% 0%
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B) ABGR2101010 1% 1% 0% 3% 0% 0% 0% 0% 0% 0% 0%
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, PIPE_XOR_BITS = 4) ABGR2101010 1% 1% 0% 3% 0% 0% 0% 0% 0% 0% 0%
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B) ABGR2101010 1% 1% 0% 3% 0% 0% 0% 0% 0% 0% 0%
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 4, PACKERS = 4) ABGR2101010 1% 3% 0% 9% 0% 0% 0% 0% 0% 0% 0%
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 4, PACKERS = 4) ABGR2101010 1% 3% 0% 9% 0% 0% 0% 0% 0% 0% 0%
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 4, PACKERS = 4) ABGR2101010 1% 2% 0% 6% 0% 0% 0% 0% 0% 0% 0%
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 4, PACKERS = 4) ABGR2101010 1% 2% 0% 6% 0% 0% 0% 0% 0% 0% 0%
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 5) ABGR2101010 1% 1% 0% 3% 0% 0% 0% 0% 0% 0% 0%
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) ABGR2101010 1% 1% 0% 3% 0% 0% 0% 0% 0% 0% 0%
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, PIPE_XOR_BITS = 5) ABGR2101010 1% 1% 0% 3% 0% 0% 0% 0% 0% 0% 0%
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B) ABGR2101010 1% 1% 0% 3% 0% 0% 0% 0% 0% 0% 0%
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, PIPE_XOR_BITS = 5) ABGR2101010 1% 1% 0% 3% 0% 0% 0% 0% 0% 0% 0%
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B) ABGR2101010 1% 1% 0% 3% 0% 0% 0% 0% 0% 0% 0%
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, PIPE_XOR_BITS = 5) ABGR2101010 1% 1% 0% 3% 0% 0% 0% 0% 0% 0% 0%
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B) ABGR2101010 1% 1% 0% 3% 0% 0% 0% 0% 0% 0% 0%
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, PIPE_XOR_BITS = 5) ABGR2101010 1% 1% 0% 3% 0% 0% 0% 0% 0% 0% 0%
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B) ABGR2101010 1% 1% 0% 3% 0% 0% 0% 0% 0% 0% 0%
AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_S_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_MAX_COMPRESSED_BLOCK = 64B, PIPE_XOR_BITS = 2, BANK_XOR_BITS = 0, RB = 1, PIPE = 2) ABGR2101010 4% 5% 0% 14% 0% 0% 0% 0% 0% 0% 0%
AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_S_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, BANK_XOR_BITS = 0, RB = 1, PIPE = 2) ABGR2101010 3% 3% 0% 9% 0% 0% 0% 0% 0% 0% 0%
NVIDIA_BLOCK_LINEAR_2D(h=0, k=254, g=0, s=1, c=0) ABGR2101010 7% 16% 0% 0% 0% 0% 41% 24% 0% 0% 0%
NVIDIA_BLOCK_LINEAR_2D(h=1, k=254, g=0, s=1, c=0) ABGR2101010 7% 16% 0% 0% 0% 0% 41% 24% 0% 0% 0%
NVIDIA_BLOCK_LINEAR_2D(h=2, k=254, g=0, s=1, c=0) ABGR2101010 7% 16% 0% 0% 0% 0% 41% 24% 0% 0% 0%
NVIDIA_BLOCK_LINEAR_2D(h=3, k=254, g=0, s=1, c=0) ABGR2101010 7% 16% 0% 0% 0% 0% 41% 24% 0% 0% 0%
NVIDIA_BLOCK_LINEAR_2D(h=4, k=254, g=0, s=1, c=0) ABGR2101010 7% 16% 0% 0% 0% 0% 41% 24% 0% 0% 0%
NVIDIA_BLOCK_LINEAR_2D(h=5, k=254, g=0, s=1, c=0) ABGR2101010 7% 16% 0% 0% 0% 0% 41% 24% 0% 0% 0%
NVIDIA_BLOCK_LINEAR_2D(h=0, k=112, g=1, s=1, c=0) ABGR2101010 0% 1% 0% 0% 0% 0% 3% 0% 0% 0% 0%
NVIDIA_BLOCK_LINEAR_2D(h=1, k=112, g=1, s=1, c=0) ABGR2101010 0% 1% 0% 0% 0% 0% 3% 0% 0% 0% 0%
NVIDIA_BLOCK_LINEAR_2D(h=2, k=112, g=1, s=1, c=0) ABGR2101010 0% 1% 0% 0% 0% 0% 3% 0% 0% 0% 0%
NVIDIA_BLOCK_LINEAR_2D(h=3, k=112, g=1, s=1, c=0) ABGR2101010 0% 1% 0% 0% 0% 0% 3% 0% 0% 0% 0%
NVIDIA_BLOCK_LINEAR_2D(h=4, k=112, g=1, s=1, c=0) ABGR2101010 0% 1% 0% 0% 0% 0% 3% 0% 0% 0% 0%
NVIDIA_BLOCK_LINEAR_2D(h=5, k=112, g=1, s=1, c=0) ABGR2101010 0% 1% 0% 0% 0% 0% 3% 0% 0% 0% 0%
NVIDIA_BLOCK_LINEAR_2D(h=0, k=120, g=1, s=1, c=0) ABGR2101010 0% 1% 0% 0% 0% 0% 3% 0% 0% 0% 0%
NVIDIA_BLOCK_LINEAR_2D(h=1, k=120, g=1, s=1, c=0) ABGR2101010 0% 1% 0% 0% 0% 0% 3% 0% 0% 0% 0%
NVIDIA_BLOCK_LINEAR_2D(h=2, k=120, g=1, s=1, c=0) ABGR2101010 0% 1% 0% 0% 0% 0% 3% 0% 0% 0% 0%
NVIDIA_BLOCK_LINEAR_2D(h=3, k=120, g=1, s=1, c=0) ABGR2101010 0% 1% 0% 0% 0% 0% 3% 0% 0% 0% 0%
NVIDIA_BLOCK_LINEAR_2D(h=4, k=120, g=1, s=1, c=0) ABGR2101010 0% 1% 0% 0% 0% 0% 3% 0% 0% 0% 0%
NVIDIA_BLOCK_LINEAR_2D(h=5, k=120, g=1, s=1, c=0) ABGR2101010 0% 1% 0% 0% 0% 0% 3% 0% 0% 0% 0%
NVIDIA_BLOCK_LINEAR_2D(h=0, k=122, g=1, s=1, c=0) ABGR2101010 0% 1% 0% 0% 0% 0% 3% 0% 0% 0% 0%
NVIDIA_BLOCK_LINEAR_2D(h=1, k=122, g=1, s=1, c=0) ABGR2101010 0% 1% 0% 0% 0% 0% 3% 0% 0% 0% 0%
NVIDIA_BLOCK_LINEAR_2D(h=2, k=122, g=1, s=1, c=0) ABGR2101010 0% 1% 0% 0% 0% 0% 3% 0% 0% 0% 0%
NVIDIA_BLOCK_LINEAR_2D(h=3, k=122, g=1, s=1, c=0) ABGR2101010 0% 1% 0% 0% 0% 0% 3% 0% 0% 0% 0%
NVIDIA_BLOCK_LINEAR_2D(h=4, k=122, g=1, s=1, c=0) ABGR2101010 0% 1% 0% 0% 0% 0% 3% 0% 0% 0% 0%
NVIDIA_BLOCK_LINEAR_2D(h=5, k=122, g=1, s=1, c=0) ABGR2101010 0% 1% 0% 0% 0% 0% 3% 0% 0% 0% 0%
NVIDIA_BLOCK_LINEAR_2D(h=0, k=6, g=2, s=1, c=0) ABGR2101010 31% 20% 0% 0% 0% 0% 17% 76% 0% 0% 0%
NVIDIA_BLOCK_LINEAR_2D(h=1, k=6, g=2, s=1, c=0) ABGR2101010 31% 20% 0% 0% 0% 0% 17% 76% 0% 0% 0%
NVIDIA_BLOCK_LINEAR_2D(h=2, k=6, g=2, s=1, c=0) ABGR2101010 31% 20% 0% 0% 0% 0% 17% 76% 0% 0% 0%
NVIDIA_BLOCK_LINEAR_2D(h=3, k=6, g=2, s=1, c=0) ABGR2101010 31% 20% 0% 0% 0% 0% 17% 76% 0% 0% 0%
NVIDIA_BLOCK_LINEAR_2D(h=4, k=6, g=2, s=1, c=0) ABGR2101010 31% 20% 0% 0% 0% 0% 17% 76% 0% 0% 0%
NVIDIA_BLOCK_LINEAR_2D(h=5, k=6, g=2, s=1, c=0) ABGR2101010 31% 20% 0% 0% 0% 0% 17% 76% 0% 0% 0%
ARM_AFBC(BLOCK_SIZE = 16x16) ABGR2101010 1% 0% 0% 0% 0% 0% 0% 0% 100% 0% 0%
ARM_AFBC(BLOCK_SIZE = 16x16, YTR) ABGR2101010 1% 0% 0% 0% 0% 0% 0% 0% 100% 0% 0%
ARM_AFBC(BLOCK_SIZE = 16x16, SPARSE) ABGR2101010 1% 0% 0% 0% 0% 0% 0% 0% 100% 0% 0%
ARM_AFBC(BLOCK_SIZE = 16x16, YTR, SPARSE) ABGR2101010 1% 0% 0% 0% 0% 0% 0% 0% 100% 0% 0%
ARM_AFBC(BLOCK_SIZE = 16x16, YTR, SPLIT, SPARSE) ABGR2101010 1% 0% 0% 0% 0% 0% 0% 0% 100% 0% 0%
ARM_AFBC(BLOCK_SIZE = 16x16, CBR) ABGR2101010 1% 0% 0% 0% 0% 0% 0% 0% 100% 0% 0%
ARM_AFBC(BLOCK_SIZE = 16x16, YTR, CBR) ABGR2101010 1% 0% 0% 0% 0% 0% 0% 0% 100% 0% 0%
ARM_AFBC(BLOCK_SIZE = 16x16, SPARSE, CBR) ABGR2101010 1% 0% 0% 0% 0% 0% 0% 0% 100% 0% 0%
ARM_AFBC(BLOCK_SIZE = 16x16, YTR, SPARSE, CBR) ABGR2101010 1% 0% 0% 0% 0% 0% 0% 0% 100% 0% 0%
unknown ABGR2101010 1% 1% 0% 0% 0% 0% 0% 0% 0% 100% 0%
unknown ABGR2101010 1% 1% 0% 0% 0% 0% 0% 0% 0% 100% 0%
unknown ABGR2101010 1% 1% 0% 0% 0% 0% 0% 0% 0% 100% 0%
unknown ABGR2101010 1% 1% 0% 0% 0% 0% 0% 0% 0% 100% 0%
unknown ABGR2101010 1% 1% 0% 0% 0% 0% 0% 0% 0% 100% 0%
unknown ABGR2101010 1% 1% 0% 0% 0% 0% 0% 0% 0% 100% 0%
unknown ABGR2101010 1% 1% 0% 0% 0% 0% 0% 0% 0% 100% 0%