DRM database formats

Back to index

Filters: XBGR16161616 ×

Input formats

The percentages indicate the number of devices supporting the format and modifier. For instance, "50%" in the column for the "i915" driver would mean that half the known Intel devices support that format and modifier.

Modifier Format Planes Drivers
overlay primary amdgpu
LINEAR XBGR16161616 100% 100% 100%
AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_S) XBGR16161616 75% 52% 52%
AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_D) XBGR16161616 75% 55% 55%
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_D) XBGR16161616 25% 12% 12%
AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 2, BANK_XOR_BITS = 0) XBGR16161616 25% 15% 15%
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 2, PACKERS = 0) XBGR16161616 8% 3% 3%
AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_D_X, PIPE_XOR_BITS = 2, BANK_XOR_BITS = 0) XBGR16161616 25% 15% 15%
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2, PACKERS = 0) XBGR16161616 8% 3% 3%
AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 3) XBGR16161616 8% 3% 3%
AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 3) XBGR16161616 8% 3% 3%
AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 4) XBGR16161616 0% 3% 3%
AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4) XBGR16161616 0% 3% 3%
AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_D_X, PIPE_XOR_BITS = 4, BANK_XOR_BITS = 4) XBGR16161616 0% 3% 3%
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 2, PACKERS = 1) XBGR16161616 8% 3% 3%
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2, PACKERS = 1) XBGR16161616 8% 3% 3%
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 2, PACKERS = 2) XBGR16161616 8% 6% 6%
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2, PACKERS = 2) XBGR16161616 8% 6% 6%
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2) XBGR16161616 8% 3% 3%
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) XBGR16161616 8% 3% 3%
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 3, PACKERS = 3) XBGR16161616 8% 6% 6%
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 3, PACKERS = 3) XBGR16161616 8% 6% 6%
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 3) XBGR16161616 0% 3% 3%
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) XBGR16161616 0% 3% 3%
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 4, PACKERS = 3) XBGR16161616 8% 3% 3%
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4, PACKERS = 3) XBGR16161616 8% 3% 3%
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 4, PACKERS = 4) XBGR16161616 0% 9% 9%
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4, PACKERS = 4) XBGR16161616 0% 9% 9%
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4) XBGR16161616 8% 3% 3%
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) XBGR16161616 8% 3% 3%
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 5) XBGR16161616 8% 3% 3%
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) XBGR16161616 8% 3% 3%