DRM database formats

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Filters: XBGR16161616 ×

Input formats

The percentages indicate the number of devices supporting the format and modifier. For instance, "50%" in the column for the "i915" driver would mean that half the known Intel devices support that format and modifier.

Modifier Format Planes Drivers
overlay primary amdgpu
LINEAR XBGR16161616 100% 100% 100%
AMD(TILE_VERSION = unknown, TILE = unknown) XBGR16161616 4% 2% 2%
AMD(TILE_VERSION = unknown, TILE = unknown) XBGR16161616 4% 2% 2%
AMD(TILE_VERSION = unknown, TILE = unknown) XBGR16161616 4% 2% 2%
AMD(TILE_VERSION = unknown, TILE = unknown) XBGR16161616 4% 2% 2%
AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_S) XBGR16161616 70% 50% 50%
AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_D) XBGR16161616 70% 52% 52%
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_D) XBGR16161616 26% 15% 15%
AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 64B) XBGR16161616 4% 2% 2%
AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 64B) XBGR16161616 4% 2% 2%
AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 64B) XBGR16161616 4% 2% 2%
AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 64B) XBGR16161616 4% 2% 2%
AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 128B) XBGR16161616 4% 2% 2%
AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 128B) XBGR16161616 4% 2% 2%
AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 128B) XBGR16161616 4% 2% 2%
AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 128B) XBGR16161616 4% 2% 2%
AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 256B) XBGR16161616 4% 2% 2%
AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 256B) XBGR16161616 4% 2% 2%
AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 256B) XBGR16161616 4% 2% 2%
AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 256B) XBGR16161616 4% 2% 2%
AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 2, BANK_XOR_BITS = 0) XBGR16161616 22% 15% 15%
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 2, PACKERS = 0) XBGR16161616 9% 5% 5%
AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_D_X, PIPE_XOR_BITS = 2, BANK_XOR_BITS = 0) XBGR16161616 22% 15% 15%
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2, PACKERS = 0) XBGR16161616 9% 5% 5%
AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 3) XBGR16161616 4% 2% 2%
AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 3) XBGR16161616 4% 2% 2%
AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 4) XBGR16161616 4% 2% 2%
AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4) XBGR16161616 4% 2% 2%
AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_D_X, PIPE_XOR_BITS = 4, BANK_XOR_BITS = 4) XBGR16161616 0% 2% 2%
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 2, PACKERS = 1) XBGR16161616 4% 5% 5%
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2, PACKERS = 1) XBGR16161616 4% 5% 5%
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 2, PACKERS = 2) XBGR16161616 9% 5% 5%
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2, PACKERS = 2) XBGR16161616 9% 5% 5%
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2) XBGR16161616 13% 8% 8%
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) XBGR16161616 13% 8% 8%
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 3, PACKERS = 3) XBGR16161616 9% 5% 5%
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 3, PACKERS = 3) XBGR16161616 9% 5% 5%
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 3) XBGR16161616 4% 2% 2%
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) XBGR16161616 4% 2% 2%
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 4, PACKERS = 3) XBGR16161616 4% 2% 2%
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4, PACKERS = 3) XBGR16161616 4% 2% 2%
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 4, PACKERS = 4) XBGR16161616 4% 8% 8%
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4, PACKERS = 4) XBGR16161616 4% 8% 8%
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4) XBGR16161616 4% 2% 2%
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) XBGR16161616 4% 2% 2%
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 5) XBGR16161616 4% 2% 2%
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) XBGR16161616 4% 2% 2%