| LINEAR |
ABGR16161616F |
100% |
99% |
100% |
100% |
96% |
100% |
| I915_X_TILED |
ABGR16161616F |
36% |
22% |
0% |
100% |
0% |
0% |
| I915_Y_TILED |
ABGR16161616F |
27% |
16% |
0% |
75% |
0% |
0% |
| I915_4_TILED |
ABGR16161616F |
9% |
5% |
0% |
25% |
0% |
0% |
| AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_S) |
ABGR16161616F |
23% |
19% |
53% |
0% |
0% |
0% |
| AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_D) |
ABGR16161616F |
23% |
20% |
56% |
0% |
0% |
0% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_D) |
ABGR16161616F |
7% |
4% |
12% |
0% |
0% |
0% |
| AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 2, BANK_XOR_BITS = 0) |
ABGR16161616F |
7% |
5% |
15% |
0% |
0% |
0% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 2, PACKERS = 0) |
ABGR16161616F |
2% |
1% |
3% |
0% |
0% |
0% |
| AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_D_X, PIPE_XOR_BITS = 2, BANK_XOR_BITS = 0) |
ABGR16161616F |
7% |
5% |
15% |
0% |
0% |
0% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2, PACKERS = 0) |
ABGR16161616F |
2% |
1% |
3% |
0% |
0% |
0% |
| AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 3) |
ABGR16161616F |
2% |
1% |
3% |
0% |
0% |
0% |
| AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 3) |
ABGR16161616F |
2% |
1% |
3% |
0% |
0% |
0% |
| AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 4) |
ABGR16161616F |
2% |
1% |
3% |
0% |
0% |
0% |
| AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4) |
ABGR16161616F |
2% |
1% |
3% |
0% |
0% |
0% |
| AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_D_X, PIPE_XOR_BITS = 4, BANK_XOR_BITS = 4) |
ABGR16161616F |
0% |
1% |
3% |
0% |
0% |
0% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 2, PACKERS = 1) |
ABGR16161616F |
2% |
2% |
6% |
0% |
0% |
0% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2, PACKERS = 1) |
ABGR16161616F |
2% |
2% |
6% |
0% |
0% |
0% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 2, PACKERS = 2) |
ABGR16161616F |
2% |
2% |
6% |
0% |
0% |
0% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2, PACKERS = 2) |
ABGR16161616F |
2% |
2% |
6% |
0% |
0% |
0% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2) |
ABGR16161616F |
2% |
1% |
3% |
0% |
0% |
0% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) |
ABGR16161616F |
2% |
1% |
3% |
0% |
0% |
0% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 3, PACKERS = 3) |
ABGR16161616F |
4% |
2% |
6% |
0% |
0% |
0% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 3, PACKERS = 3) |
ABGR16161616F |
4% |
2% |
6% |
0% |
0% |
0% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 3) |
ABGR16161616F |
2% |
1% |
3% |
0% |
0% |
0% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) |
ABGR16161616F |
2% |
1% |
3% |
0% |
0% |
0% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 4, PACKERS = 3) |
ABGR16161616F |
2% |
1% |
3% |
0% |
0% |
0% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4, PACKERS = 3) |
ABGR16161616F |
2% |
1% |
3% |
0% |
0% |
0% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 4, PACKERS = 4) |
ABGR16161616F |
2% |
3% |
9% |
0% |
0% |
0% |
| AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4, PACKERS = 4) |
ABGR16161616F |
2% |
3% |
9% |
0% |
0% |
0% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4) |
ABGR16161616F |
2% |
1% |
3% |
0% |
0% |
0% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) |
ABGR16161616F |
2% |
1% |
3% |
0% |
0% |
0% |
| AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 5) |
ABGR16161616F |
2% |
1% |
3% |
0% |
0% |
0% |
| AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) |
ABGR16161616F |
2% |
1% |
3% |
0% |
0% |
0% |
| NVIDIA_BLOCK_LINEAR_2D(h=0, k=254, g=0, s=1, c=0) |
ABGR16161616F |
4% |
16% |
0% |
0% |
50% |
15% |
| NVIDIA_BLOCK_LINEAR_2D(h=1, k=254, g=0, s=1, c=0) |
ABGR16161616F |
4% |
16% |
0% |
0% |
50% |
15% |
| NVIDIA_BLOCK_LINEAR_2D(h=2, k=254, g=0, s=1, c=0) |
ABGR16161616F |
4% |
16% |
0% |
0% |
50% |
15% |
| NVIDIA_BLOCK_LINEAR_2D(h=3, k=254, g=0, s=1, c=0) |
ABGR16161616F |
4% |
16% |
0% |
0% |
50% |
15% |
| NVIDIA_BLOCK_LINEAR_2D(h=4, k=254, g=0, s=1, c=0) |
ABGR16161616F |
4% |
16% |
0% |
0% |
50% |
15% |
| NVIDIA_BLOCK_LINEAR_2D(h=5, k=254, g=0, s=1, c=0) |
ABGR16161616F |
4% |
16% |
0% |
0% |
50% |
15% |
| NVIDIA_BLOCK_LINEAR_2D(h=0, k=112, g=1, s=1, c=0) |
ABGR16161616F |
0% |
1% |
0% |
0% |
4% |
0% |
| NVIDIA_BLOCK_LINEAR_2D(h=1, k=112, g=1, s=1, c=0) |
ABGR16161616F |
0% |
1% |
0% |
0% |
4% |
0% |
| NVIDIA_BLOCK_LINEAR_2D(h=2, k=112, g=1, s=1, c=0) |
ABGR16161616F |
0% |
1% |
0% |
0% |
4% |
0% |
| NVIDIA_BLOCK_LINEAR_2D(h=3, k=112, g=1, s=1, c=0) |
ABGR16161616F |
0% |
1% |
0% |
0% |
4% |
0% |
| NVIDIA_BLOCK_LINEAR_2D(h=4, k=112, g=1, s=1, c=0) |
ABGR16161616F |
0% |
1% |
0% |
0% |
4% |
0% |
| NVIDIA_BLOCK_LINEAR_2D(h=5, k=112, g=1, s=1, c=0) |
ABGR16161616F |
0% |
1% |
0% |
0% |
4% |
0% |
| NVIDIA_BLOCK_LINEAR_2D(h=0, k=6, g=2, s=1, c=0) |
ABGR16161616F |
29% |
17% |
0% |
0% |
19% |
85% |
| NVIDIA_BLOCK_LINEAR_2D(h=1, k=6, g=2, s=1, c=0) |
ABGR16161616F |
29% |
17% |
0% |
0% |
19% |
85% |
| NVIDIA_BLOCK_LINEAR_2D(h=2, k=6, g=2, s=1, c=0) |
ABGR16161616F |
29% |
17% |
0% |
0% |
19% |
85% |
| NVIDIA_BLOCK_LINEAR_2D(h=3, k=6, g=2, s=1, c=0) |
ABGR16161616F |
29% |
17% |
0% |
0% |
19% |
85% |
| NVIDIA_BLOCK_LINEAR_2D(h=4, k=6, g=2, s=1, c=0) |
ABGR16161616F |
29% |
17% |
0% |
0% |
19% |
85% |
| NVIDIA_BLOCK_LINEAR_2D(h=5, k=6, g=2, s=1, c=0) |
ABGR16161616F |
29% |
17% |
0% |
0% |
19% |
85% |