DRM database formats

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Filters: XRGB16161616F ×

Input formats

The percentages indicate the number of devices supporting the format and modifier. For instance, "50%" in the column for the "i915" driver would mean that half the known Intel devices support that format and modifier.

Modifier Format Planes Drivers
overlay primary amdgpu i915
LINEAR XRGB16161616F 100% 100% 100% 100%
I915_X_TILED XRGB16161616F 82% 52% 0% 100%
I915_Y_TILED XRGB16161616F 56% 47% 0% 69%
I915_4_TILED XRGB16161616F 5% 5% 0% 7%
AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_S) XRGB16161616F 13% 24% 50% 0%
AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_D) XRGB16161616F 13% 26% 53% 0%
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_D) XRGB16161616F 5% 6% 12% 0%
AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 2, BANK_XOR_BITS = 0) XRGB16161616F 5% 8% 16% 0%
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 2, PACKERS = 0) XRGB16161616F 2% 2% 3% 0%
AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_D_X, PIPE_XOR_BITS = 2, BANK_XOR_BITS = 0) XRGB16161616F 5% 8% 16% 0%
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2, PACKERS = 0) XRGB16161616F 2% 2% 3% 0%
AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 3) XRGB16161616F 0% 2% 3% 0%
AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 3) XRGB16161616F 0% 2% 3% 0%
AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 4) XRGB16161616F 0% 2% 3% 0%
AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4) XRGB16161616F 0% 2% 3% 0%
AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_D_X, PIPE_XOR_BITS = 4, BANK_XOR_BITS = 4) XRGB16161616F 0% 2% 3% 0%
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 2, PACKERS = 2) XRGB16161616F 2% 3% 6% 0%
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2, PACKERS = 2) XRGB16161616F 2% 3% 6% 0%
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2) XRGB16161616F 2% 2% 3% 0%
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) XRGB16161616F 2% 2% 3% 0%
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 3, PACKERS = 3) XRGB16161616F 2% 3% 6% 0%
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 3, PACKERS = 3) XRGB16161616F 2% 3% 6% 0%
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 3) XRGB16161616F 0% 2% 3% 0%
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) XRGB16161616F 0% 2% 3% 0%
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 4, PACKERS = 3) XRGB16161616F 2% 2% 3% 0%
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4, PACKERS = 3) XRGB16161616F 2% 2% 3% 0%
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 4, PACKERS = 4) XRGB16161616F 0% 5% 9% 0%
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4, PACKERS = 4) XRGB16161616F 0% 5% 9% 0%
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4) XRGB16161616F 2% 2% 3% 0%
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) XRGB16161616F 2% 2% 3% 0%
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 5) XRGB16161616F 2% 2% 3% 0%
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) XRGB16161616F 2% 2% 3% 0%