DRM database formats

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Filters: XRGB16161616F ×

Input formats

The percentages indicate the number of devices supporting the format and modifier. For instance, "50%" in the column for the "i915" driver would mean that half the known Intel devices support that format and modifier.

Modifier	Format	Planes		Drivers
		overlay	primary	amdgpu	i915	xe
LINEAR	XRGB16161616F	100%	100%	100%	100%	100%
I915_X_TILED	XRGB16161616F	73%	55%	0%	100%	100%
I915_Y_TILED	XRGB16161616F	47%	45%	0%	66%	0%
I915_4_TILED	XRGB16161616F	10%	10%	0%	12%	100%
I915_4_TILED_MTL_RC_CCS	XRGB16161616F	1%	1%	0%	2%	0%
I915_4_TILED_MTL_MC_CCS	XRGB16161616F	1%	1%	0%	2%	0%
I915_4_TILED_MTL_RC_CCS_CC	XRGB16161616F	1%	1%	0%	2%	0%
INTEL(unknown)	XRGB16161616F	1%	1%	0%	0%	100%
AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_S)	XRGB16161616F	19%	23%	51%	0%	0%
AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_D)	XRGB16161616F	19%	24%	54%	0%	0%
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_D)	XRGB16161616F	8%	7%	16%	0%	0%
AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 2, BANK_XOR_BITS = 0)	XRGB16161616F	6%	7%	16%	0%	0%
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 2, PACKERS = 0)	XRGB16161616F	1%	1%	3%	0%	0%
AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_D_X, PIPE_XOR_BITS = 2, BANK_XOR_BITS = 0)	XRGB16161616F	6%	7%	16%	0%	0%
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2, PACKERS = 0)	XRGB16161616F	1%	1%	3%	0%	0%
AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 3)	XRGB16161616F	1%	1%	3%	0%	0%
AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 3)	XRGB16161616F	1%	1%	3%	0%	0%
AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 4)	XRGB16161616F	1%	1%	3%	0%	0%
AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4)	XRGB16161616F	1%	1%	3%	0%	0%
AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_D_X, PIPE_XOR_BITS = 4, BANK_XOR_BITS = 4)	XRGB16161616F	0%	1%	3%	0%	0%
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 2, PACKERS = 1)	XRGB16161616F	1%	2%	5%	0%	0%
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2, PACKERS = 1)	XRGB16161616F	1%	2%	5%	0%	0%
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 2, PACKERS = 2)	XRGB16161616F	3%	2%	5%	0%	0%
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2, PACKERS = 2)	XRGB16161616F	3%	2%	5%	0%	0%
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2)	XRGB16161616F	4%	4%	8%	0%	0%
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X)	XRGB16161616F	4%	4%	8%	0%	0%
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 3, PACKERS = 3)	XRGB16161616F	3%	2%	5%	0%	0%
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 3, PACKERS = 3)	XRGB16161616F	3%	2%	5%	0%	0%
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 3)	XRGB16161616F	1%	1%	3%	0%	0%
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X)	XRGB16161616F	1%	1%	3%	0%	0%
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 4, PACKERS = 3)	XRGB16161616F	1%	1%	3%	0%	0%
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4, PACKERS = 3)	XRGB16161616F	1%	1%	3%	0%	0%
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 4, PACKERS = 4)	XRGB16161616F	1%	4%	8%	0%	0%
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4, PACKERS = 4)	XRGB16161616F	1%	4%	8%	0%	0%
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4)	XRGB16161616F	1%	1%	3%	0%	0%
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X)	XRGB16161616F	1%	1%	3%	0%	0%
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 5)	XRGB16161616F	1%	1%	3%	0%	0%
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X)	XRGB16161616F	1%	1%	3%	0%	0%