LINEAR |
XRGB16161616F |
100% |
100% |
100% |
100% |

I915_X_TILED |
XRGB16161616F |
76% |
53% |
0% |
100% |

I915_Y_TILED |
XRGB16161616F |
51% |
47% |
0% |
67% |

I915_4_TILED |
XRGB16161616F |
7% |
7% |
0% |
10% |

AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_S) |
XRGB16161616F |
19% |
25% |
53% |
0% |

AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_D) |
XRGB16161616F |
19% |
26% |
56% |
0% |

AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_D) |
XRGB16161616F |
4% |
5% |
12% |
0% |

AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 2, BANK_XOR_BITS = 0) |
XRGB16161616F |
6% |
7% |
15% |
0% |

AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 2, PACKERS = 0) |
XRGB16161616F |
1% |
1% |
3% |
0% |

AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_D_X, PIPE_XOR_BITS = 2, BANK_XOR_BITS = 0) |
XRGB16161616F |
6% |
7% |
15% |
0% |

AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2, PACKERS = 0) |
XRGB16161616F |
1% |
1% |
3% |
0% |

AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 3) |
XRGB16161616F |
1% |
1% |
3% |
0% |

AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 3) |
XRGB16161616F |
1% |
1% |
3% |
0% |

AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 4) |
XRGB16161616F |
1% |
1% |
3% |
0% |

AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4) |
XRGB16161616F |
1% |
1% |
3% |
0% |

AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_D_X, PIPE_XOR_BITS = 4, BANK_XOR_BITS = 4) |
XRGB16161616F |
0% |
1% |
3% |
0% |

AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 2, PACKERS = 1) |
XRGB16161616F |
1% |
3% |
6% |
0% |

AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2, PACKERS = 1) |
XRGB16161616F |
1% |
3% |
6% |
0% |

AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 2, PACKERS = 2) |
XRGB16161616F |
1% |
3% |
6% |
0% |

AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2, PACKERS = 2) |
XRGB16161616F |
1% |
3% |
6% |
0% |

AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2) |
XRGB16161616F |
1% |
1% |
3% |
0% |

AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) |
XRGB16161616F |
1% |
1% |
3% |
0% |

AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 3, PACKERS = 3) |
XRGB16161616F |
3% |
3% |
6% |
0% |

AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 3, PACKERS = 3) |
XRGB16161616F |
3% |
3% |
6% |
0% |

AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 3) |
XRGB16161616F |
0% |
1% |
3% |
0% |

AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) |
XRGB16161616F |
0% |
1% |
3% |
0% |

AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 4, PACKERS = 3) |
XRGB16161616F |
1% |
1% |
3% |
0% |

AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4, PACKERS = 3) |
XRGB16161616F |
1% |
1% |
3% |
0% |

AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 4, PACKERS = 4) |
XRGB16161616F |
1% |
4% |
9% |
0% |

AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4, PACKERS = 4) |
XRGB16161616F |
1% |
4% |
9% |
0% |

AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4) |
XRGB16161616F |
1% |
1% |
3% |
0% |

AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) |
XRGB16161616F |
1% |
1% |
3% |
0% |

AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 5) |
XRGB16161616F |
1% |
1% |
3% |
0% |

AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) |
XRGB16161616F |
1% |
1% |
3% |
0% |