DRM database formats

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Filters: XRGB16161616F ×

Input formats

The percentages indicate the number of devices supporting the format and modifier. For instance, "50%" in the column for the "i915" driver would mean that half the known Intel devices support that format and modifier.

Modifier Format Planes Drivers
overlay primary amdgpu i915 xe
LINEAR XRGB16161616F 100% 100% 100% 100% 100%
I915_X_TILED XRGB16161616F 75% 56% 0% 100% 100%
I915_Y_TILED XRGB16161616F 49% 47% 0% 67% 0%
I915_4_TILED XRGB16161616F 9% 9% 0% 11% 100%
INTEL(unknown) XRGB16161616F 1% 1% 0% 0% 100%
AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_S) XRGB16161616F 19% 23% 51% 0% 0%
AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_D) XRGB16161616F 19% 24% 54% 0% 0%
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_D) XRGB16161616F 7% 6% 14% 0% 0%
AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 2, BANK_XOR_BITS = 0) XRGB16161616F 5% 6% 14% 0% 0%
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 2, PACKERS = 0) XRGB16161616F 1% 1% 3% 0% 0%
AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_D_X, PIPE_XOR_BITS = 2, BANK_XOR_BITS = 0) XRGB16161616F 5% 6% 14% 0% 0%
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2, PACKERS = 0) XRGB16161616F 1% 1% 3% 0% 0%
AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 3) XRGB16161616F 1% 1% 3% 0% 0%
AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 3) XRGB16161616F 1% 1% 3% 0% 0%
AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 4) XRGB16161616F 1% 1% 3% 0% 0%
AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4) XRGB16161616F 1% 1% 3% 0% 0%
AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_D_X, PIPE_XOR_BITS = 4, BANK_XOR_BITS = 4) XRGB16161616F 0% 1% 3% 0% 0%
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 2, PACKERS = 1) XRGB16161616F 1% 3% 6% 0% 0%
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2, PACKERS = 1) XRGB16161616F 1% 3% 6% 0% 0%
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 2, PACKERS = 2) XRGB16161616F 3% 3% 6% 0% 0%
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2, PACKERS = 2) XRGB16161616F 3% 3% 6% 0% 0%
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2) XRGB16161616F 3% 3% 6% 0% 0%
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) XRGB16161616F 3% 3% 6% 0% 0%
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 3, PACKERS = 3) XRGB16161616F 3% 3% 6% 0% 0%
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 3, PACKERS = 3) XRGB16161616F 3% 3% 6% 0% 0%
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 3) XRGB16161616F 1% 1% 3% 0% 0%
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) XRGB16161616F 1% 1% 3% 0% 0%
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 4, PACKERS = 3) XRGB16161616F 1% 1% 3% 0% 0%
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4, PACKERS = 3) XRGB16161616F 1% 1% 3% 0% 0%
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 4, PACKERS = 4) XRGB16161616F 1% 4% 9% 0% 0%
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4, PACKERS = 4) XRGB16161616F 1% 4% 9% 0% 0%
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4) XRGB16161616F 1% 1% 3% 0% 0%
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) XRGB16161616F 1% 1% 3% 0% 0%
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 5) XRGB16161616F 1% 1% 3% 0% 0%
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) XRGB16161616F 1% 1% 3% 0% 0%