DRM database formats

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Filters: XBGR16161616F ×

Input formats

The percentages indicate the number of devices supporting the format and modifier. For instance, "50%" in the column for the "i915" driver would mean that half the known Intel devices support that format and modifier.

Modifier Format Planes Drivers
overlay primary amdgpu i915 nouveau nvidia-drm
LINEAR XBGR16161616F 100% 99% 100% 100% 96% 100%
I915_X_TILED XBGR16161616F 53% 42% 0% 100% 0% 0%
I915_Y_TILED XBGR16161616F 36% 28% 0% 63% 0% 0%
I915_4_TILED XBGR16161616F 4% 3% 0% 8% 0% 0%
AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_S) XBGR16161616F 13% 15% 53% 0% 0% 0%
AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_D) XBGR16161616F 13% 16% 56% 0% 0% 0%
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_D) XBGR16161616F 3% 3% 12% 0% 0% 0%
AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 2, BANK_XOR_BITS = 0) XBGR16161616F 4% 4% 15% 0% 0% 0%
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 2, PACKERS = 0) XBGR16161616F 1% 1% 3% 0% 0% 0%
AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_D_X, PIPE_XOR_BITS = 2, BANK_XOR_BITS = 0) XBGR16161616F 4% 4% 15% 0% 0% 0%
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2, PACKERS = 0) XBGR16161616F 1% 1% 3% 0% 0% 0%
AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 3) XBGR16161616F 1% 1% 3% 0% 0% 0%
AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 3) XBGR16161616F 1% 1% 3% 0% 0% 0%
AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 4) XBGR16161616F 1% 1% 3% 0% 0% 0%
AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4) XBGR16161616F 1% 1% 3% 0% 0% 0%
AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_D_X, PIPE_XOR_BITS = 4, BANK_XOR_BITS = 4) XBGR16161616F 0% 1% 3% 0% 0% 0%
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 2, PACKERS = 1) XBGR16161616F 1% 2% 6% 0% 0% 0%
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2, PACKERS = 1) XBGR16161616F 1% 2% 6% 0% 0% 0%
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 2, PACKERS = 2) XBGR16161616F 1% 2% 6% 0% 0% 0%
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2, PACKERS = 2) XBGR16161616F 1% 2% 6% 0% 0% 0%
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2) XBGR16161616F 1% 1% 3% 0% 0% 0%
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) XBGR16161616F 1% 1% 3% 0% 0% 0%
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 3, PACKERS = 3) XBGR16161616F 1% 2% 6% 0% 0% 0%
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 3, PACKERS = 3) XBGR16161616F 1% 2% 6% 0% 0% 0%
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 3) XBGR16161616F 0% 1% 3% 0% 0% 0%
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) XBGR16161616F 0% 1% 3% 0% 0% 0%
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 4, PACKERS = 3) XBGR16161616F 1% 1% 3% 0% 0% 0%
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4, PACKERS = 3) XBGR16161616F 1% 1% 3% 0% 0% 0%
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 4, PACKERS = 4) XBGR16161616F 1% 3% 9% 0% 0% 0%
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4, PACKERS = 4) XBGR16161616F 1% 3% 9% 0% 0% 0%
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4) XBGR16161616F 1% 1% 3% 0% 0% 0%
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) XBGR16161616F 1% 1% 3% 0% 0% 0%
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 5) XBGR16161616F 1% 1% 3% 0% 0% 0%
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) XBGR16161616F 1% 1% 3% 0% 0% 0%
NVIDIA_BLOCK_LINEAR_2D(h=0, k=254, g=0, s=1, c=0) XBGR16161616F 9% 11% 0% 0% 48% 10%
NVIDIA_BLOCK_LINEAR_2D(h=1, k=254, g=0, s=1, c=0) XBGR16161616F 9% 11% 0% 0% 48% 10%
NVIDIA_BLOCK_LINEAR_2D(h=2, k=254, g=0, s=1, c=0) XBGR16161616F 9% 11% 0% 0% 48% 10%
NVIDIA_BLOCK_LINEAR_2D(h=3, k=254, g=0, s=1, c=0) XBGR16161616F 9% 11% 0% 0% 48% 10%
NVIDIA_BLOCK_LINEAR_2D(h=4, k=254, g=0, s=1, c=0) XBGR16161616F 9% 11% 0% 0% 48% 10%
NVIDIA_BLOCK_LINEAR_2D(h=5, k=254, g=0, s=1, c=0) XBGR16161616F 9% 11% 0% 0% 48% 10%
NVIDIA_BLOCK_LINEAR_2D(h=0, k=112, g=1, s=1, c=0) XBGR16161616F 0% 1% 0% 0% 4% 0%
NVIDIA_BLOCK_LINEAR_2D(h=1, k=112, g=1, s=1, c=0) XBGR16161616F 0% 1% 0% 0% 4% 0%
NVIDIA_BLOCK_LINEAR_2D(h=2, k=112, g=1, s=1, c=0) XBGR16161616F 0% 1% 0% 0% 4% 0%
NVIDIA_BLOCK_LINEAR_2D(h=3, k=112, g=1, s=1, c=0) XBGR16161616F 0% 1% 0% 0% 4% 0%
NVIDIA_BLOCK_LINEAR_2D(h=4, k=112, g=1, s=1, c=0) XBGR16161616F 0% 1% 0% 0% 4% 0%
NVIDIA_BLOCK_LINEAR_2D(h=5, k=112, g=1, s=1, c=0) XBGR16161616F 0% 1% 0% 0% 4% 0%
NVIDIA_BLOCK_LINEAR_2D(h=0, k=6, g=2, s=1, c=0) XBGR16161616F 15% 12% 0% 0% 20% 90%
NVIDIA_BLOCK_LINEAR_2D(h=1, k=6, g=2, s=1, c=0) XBGR16161616F 15% 12% 0% 0% 20% 90%
NVIDIA_BLOCK_LINEAR_2D(h=2, k=6, g=2, s=1, c=0) XBGR16161616F 15% 12% 0% 0% 20% 90%
NVIDIA_BLOCK_LINEAR_2D(h=3, k=6, g=2, s=1, c=0) XBGR16161616F 15% 12% 0% 0% 20% 90%
NVIDIA_BLOCK_LINEAR_2D(h=4, k=6, g=2, s=1, c=0) XBGR16161616F 15% 12% 0% 0% 20% 90%
NVIDIA_BLOCK_LINEAR_2D(h=5, k=6, g=2, s=1, c=0) XBGR16161616F 15% 12% 0% 0% 20% 90%