DRM database formats

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Filters: ABGR8888 ×

Input formats

The percentages indicate the number of devices supporting the format and modifier. For instance, "50%" in the column for the "i915" driver would mean that half the known Intel devices support that format and modifier.

Modifier Format Planes Drivers
overlay primary cursor amdgpu apple evdi i915 imx-dcss imx-drm kirin mediatek meson msm nouveau nvidia-drm rockchip starfive sun4i-drm tegra vc4 xlnx
LINEAR ABGR8888 100% 100% 100% 100% 100% 100% 100% 100% 100% 100% 100% 100% 100% 100% 100% 100% 100% 100% 100% 100% 100%
I915_X_TILED ABGR8888 47% 31% 0% 0% 0% 0% 100% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0%
I915_Y_TILED ABGR8888 40% 27% 0% 0% 0% 0% 86% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0%
I915_Yf_TILED ABGR8888 32% 21% 0% 0% 0% 0% 68% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0%
I915_Y_TILED_CCS ABGR8888 32% 21% 0% 0% 0% 0% 68% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0%
I915_Yf_TILED_CCS ABGR8888 32% 21% 0% 0% 0% 0% 68% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0%
I915_Y_TILED_GEN12_RC_CCS ABGR8888 9% 6% 0% 0% 0% 0% 18% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0%
I915_Y_TILED_GEN12_MC_CCS ABGR8888 6% 4% 0% 0% 0% 0% 14% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0%
I915_Y_TILED_GEN12_RC_CCS_CC ABGR8888 9% 6% 0% 0% 0% 0% 18% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0%
I915_4_TILED ABGR8888 3% 2% 0% 0% 0% 0% 7% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0%
I915_4_TILED_DG2_RC_CCS ABGR8888 3% 2% 0% 0% 0% 0% 7% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0%
I915_4_TILED_DG2_MC_CCS ABGR8888 3% 2% 0% 0% 0% 0% 7% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0%
I915_4_TILED_DG2_RC_CCS_CC ABGR8888 3% 2% 0% 0% 0% 0% 7% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0%
AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_S) ABGR8888 17% 11% 0% 47% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0%
AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_D) ABGR8888 0% 1% 0% 3% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0%
AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 2, BANK_XOR_BITS = 0) ABGR8888 5% 4% 0% 15% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0%
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 2, PACKERS = 0) ABGR8888 1% 1% 0% 3% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0%
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2, PACKERS = 0) ABGR8888 1% 1% 0% 3% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0%
AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_S_X, DCC, DCC_INDEPENDENT_64B, DCC_MAX_COMPRESSED_BLOCK = 64B, PIPE_XOR_BITS = 2, BANK_XOR_BITS = 0, RB = 0) ABGR8888 5% 4% 0% 15% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0%
AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_S_X, DCC, DCC_INDEPENDENT_64B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, BANK_XOR_BITS = 0, RB = 0) ABGR8888 3% 2% 0% 9% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0%
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, PACKERS = 0) ABGR8888 1% 1% 0% 3% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0%
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, PACKERS = 0) ABGR8888 1% 1% 0% 3% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0%
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, PACKERS = 0) ABGR8888 1% 1% 0% 3% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0%
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, PACKERS = 0) ABGR8888 1% 1% 0% 3% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0%
AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 3) ABGR8888 1% 1% 0% 3% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0%
AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 3) ABGR8888 1% 1% 0% 3% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0%
AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 3) ABGR8888 1% 1% 0% 3% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0%
AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 3) ABGR8888 1% 1% 0% 3% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0%
AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 4) ABGR8888 1% 1% 0% 3% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0%
AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4) ABGR8888 1% 1% 0% 3% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0%
AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 4) ABGR8888 1% 1% 0% 3% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0%
AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 4) ABGR8888 1% 1% 0% 3% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0%
AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_D_X, PIPE_XOR_BITS = 4, BANK_XOR_BITS = 4) ABGR8888 0% 1% 0% 3% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0%
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 2, PACKERS = 2) ABGR8888 2% 1% 0% 6% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0%
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2, PACKERS = 2) ABGR8888 2% 1% 0% 6% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0%
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2) ABGR8888 1% 1% 0% 3% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0%
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) ABGR8888 1% 1% 0% 3% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0%
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, PIPE_XOR_BITS = 2) ABGR8888 1% 1% 0% 3% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0%
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B) ABGR8888 1% 1% 0% 3% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0%
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, PIPE_XOR_BITS = 2) ABGR8888 1% 1% 0% 3% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0%
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B) ABGR8888 1% 1% 0% 3% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0%
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, PIPE_XOR_BITS = 2) ABGR8888 1% 1% 0% 3% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0%
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B) ABGR8888 1% 1% 0% 3% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0%
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, PIPE_XOR_BITS = 2) ABGR8888 1% 1% 0% 3% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0%
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B) ABGR8888 1% 1% 0% 3% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0%
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, PACKERS = 2) ABGR8888 2% 1% 0% 6% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0%
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, PACKERS = 2) ABGR8888 2% 1% 0% 6% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0%
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, PACKERS = 2) ABGR8888 2% 1% 0% 6% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0%
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, PACKERS = 2) ABGR8888 2% 1% 0% 6% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0%
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 3, PACKERS = 3) ABGR8888 2% 1% 0% 6% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0%
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 3, PACKERS = 3) ABGR8888 2% 1% 0% 6% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0%
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 3) ABGR8888 1% 1% 0% 3% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0%
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) ABGR8888 1% 1% 0% 3% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0%
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, PIPE_XOR_BITS = 3) ABGR8888 1% 1% 0% 3% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0%
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B) ABGR8888 1% 1% 0% 3% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0%
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, PIPE_XOR_BITS = 3) ABGR8888 1% 1% 0% 3% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0%
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B) ABGR8888 1% 1% 0% 3% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0%
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, PIPE_XOR_BITS = 3) ABGR8888 1% 1% 0% 3% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0%
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B) ABGR8888 1% 1% 0% 3% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0%
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, PIPE_XOR_BITS = 3) ABGR8888 1% 1% 0% 3% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0%
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B) ABGR8888 1% 1% 0% 3% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0%
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 3, PACKERS = 3) ABGR8888 2% 1% 0% 6% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0%
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 3, PACKERS = 3) ABGR8888 2% 1% 0% 6% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0%
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 3, PACKERS = 3) ABGR8888 2% 1% 0% 6% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0%
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 3, PACKERS = 3) ABGR8888 2% 1% 0% 6% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0%
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 4, PACKERS = 3) ABGR8888 1% 1% 0% 3% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0%
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4, PACKERS = 3) ABGR8888 1% 1% 0% 3% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0%
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 4, PACKERS = 3) ABGR8888 1% 1% 0% 3% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0%
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 4, PACKERS = 3) ABGR8888 1% 1% 0% 3% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0%
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 4, PACKERS = 3) ABGR8888 1% 1% 0% 3% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0%
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 4, PACKERS = 3) ABGR8888 1% 1% 0% 3% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0%
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 4, PACKERS = 4) ABGR8888 3% 2% 0% 9% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0%
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4, PACKERS = 4) ABGR8888 3% 2% 0% 9% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0%
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4) ABGR8888 1% 1% 0% 3% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0%
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) ABGR8888 1% 1% 0% 3% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0%
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, PIPE_XOR_BITS = 4) ABGR8888 1% 1% 0% 3% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0%
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B) ABGR8888 1% 1% 0% 3% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0%
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, PIPE_XOR_BITS = 4) ABGR8888 1% 1% 0% 3% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0%
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B) ABGR8888 1% 1% 0% 3% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0%
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, PIPE_XOR_BITS = 4) ABGR8888 1% 1% 0% 3% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0%
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B) ABGR8888 1% 1% 0% 3% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0%
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, PIPE_XOR_BITS = 4) ABGR8888 1% 1% 0% 3% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0%
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B) ABGR8888 1% 1% 0% 3% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0%
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 4, PACKERS = 4) ABGR8888 3% 2% 0% 9% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0%
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 4, PACKERS = 4) ABGR8888 3% 2% 0% 9% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0%
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 4, PACKERS = 4) ABGR8888 2% 1% 0% 6% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0%
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 4, PACKERS = 4) ABGR8888 2% 1% 0% 6% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0%
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 5) ABGR8888 1% 1% 0% 3% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0%
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) ABGR8888 1% 1% 0% 3% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0%
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, PIPE_XOR_BITS = 5) ABGR8888 1% 1% 0% 3% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0%
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B) ABGR8888 1% 1% 0% 3% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0%
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B, PIPE_XOR_BITS = 5) ABGR8888 1% 1% 0% 3% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0%
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 64B) ABGR8888 1% 1% 0% 3% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0%
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, PIPE_XOR_BITS = 5) ABGR8888 1% 1% 0% 3% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0%
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B) ABGR8888 1% 1% 0% 3% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0%
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B, PIPE_XOR_BITS = 5) ABGR8888 1% 1% 0% 3% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0%
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X, DCC, DCC_RETILE, DCC_INDEPENDENT_128B, DCC_MAX_COMPRESSED_BLOCK = 128B) ABGR8888 1% 1% 0% 3% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0%
AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_S_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_MAX_COMPRESSED_BLOCK = 64B, PIPE_XOR_BITS = 2, BANK_XOR_BITS = 0, RB = 1, PIPE = 2) ABGR8888 5% 4% 0% 15% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0%
AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_S_X, DCC, DCC_RETILE, DCC_INDEPENDENT_64B, DCC_MAX_COMPRESSED_BLOCK = 64B, DCC_CONSTANT_ENCODE, PIPE_XOR_BITS = 2, BANK_XOR_BITS = 0, RB = 1, PIPE = 2) ABGR8888 3% 2% 0% 9% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0%
NVIDIA_BLOCK_LINEAR_2D(h=0, k=0, g=0, s=0, c=0) ABGR8888 0% 1% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 100% 0% 0%
NVIDIA_BLOCK_LINEAR_2D(h=1, k=0, g=0, s=0, c=0) ABGR8888 0% 1% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 100% 0% 0%
NVIDIA_BLOCK_LINEAR_2D(h=2, k=0, g=0, s=0, c=0) ABGR8888 0% 1% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 100% 0% 0%
NVIDIA_BLOCK_LINEAR_2D(h=3, k=0, g=0, s=0, c=0) ABGR8888 0% 1% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 100% 0% 0%
NVIDIA_BLOCK_LINEAR_2D(h=4, k=0, g=0, s=0, c=0) ABGR8888 0% 1% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 100% 0% 0%
NVIDIA_BLOCK_LINEAR_2D(h=5, k=0, g=0, s=0, c=0) ABGR8888 0% 1% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 100% 0% 0%
NVIDIA_BLOCK_LINEAR_2D(h=0, k=254, g=0, s=1, c=0) ABGR8888 0% 10% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 43% 15% 0% 0% 0% 0% 0% 0%
NVIDIA_BLOCK_LINEAR_2D(h=1, k=254, g=0, s=1, c=0) ABGR8888 0% 10% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 43% 15% 0% 0% 0% 0% 0% 0%
NVIDIA_BLOCK_LINEAR_2D(h=2, k=254, g=0, s=1, c=0) ABGR8888 0% 10% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 43% 15% 0% 0% 0% 0% 0% 0%
NVIDIA_BLOCK_LINEAR_2D(h=3, k=254, g=0, s=1, c=0) ABGR8888 0% 10% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 43% 15% 0% 0% 0% 0% 0% 0%
NVIDIA_BLOCK_LINEAR_2D(h=4, k=254, g=0, s=1, c=0) ABGR8888 0% 10% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 43% 15% 0% 0% 0% 0% 0% 0%
NVIDIA_BLOCK_LINEAR_2D(h=5, k=254, g=0, s=1, c=0) ABGR8888 0% 10% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 43% 15% 0% 0% 0% 0% 0% 0%
NVIDIA_BLOCK_LINEAR_2D(h=0, k=112, g=1, s=1, c=0) ABGR8888 0% 1% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 4% 0% 0% 0% 0% 0% 0% 0%
NVIDIA_BLOCK_LINEAR_2D(h=1, k=112, g=1, s=1, c=0) ABGR8888 0% 1% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 4% 0% 0% 0% 0% 0% 0% 0%
NVIDIA_BLOCK_LINEAR_2D(h=2, k=112, g=1, s=1, c=0) ABGR8888 0% 1% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 4% 0% 0% 0% 0% 0% 0% 0%
NVIDIA_BLOCK_LINEAR_2D(h=3, k=112, g=1, s=1, c=0) ABGR8888 0% 1% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 4% 0% 0% 0% 0% 0% 0% 0%
NVIDIA_BLOCK_LINEAR_2D(h=4, k=112, g=1, s=1, c=0) ABGR8888 0% 1% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 4% 0% 0% 0% 0% 0% 0% 0%
NVIDIA_BLOCK_LINEAR_2D(h=5, k=112, g=1, s=1, c=0) ABGR8888 0% 1% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 4% 0% 0% 0% 0% 0% 0% 0%
NVIDIA_BLOCK_LINEAR_2D(h=0, k=120, g=1, s=1, c=0) ABGR8888 0% 1% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 4% 0% 0% 0% 0% 0% 0% 0%
NVIDIA_BLOCK_LINEAR_2D(h=1, k=120, g=1, s=1, c=0) ABGR8888 0% 1% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 4% 0% 0% 0% 0% 0% 0% 0%
NVIDIA_BLOCK_LINEAR_2D(h=2, k=120, g=1, s=1, c=0) ABGR8888 0% 1% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 4% 0% 0% 0% 0% 0% 0% 0%
NVIDIA_BLOCK_LINEAR_2D(h=3, k=120, g=1, s=1, c=0) ABGR8888 0% 1% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 4% 0% 0% 0% 0% 0% 0% 0%
NVIDIA_BLOCK_LINEAR_2D(h=4, k=120, g=1, s=1, c=0) ABGR8888 0% 1% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 4% 0% 0% 0% 0% 0% 0% 0%
NVIDIA_BLOCK_LINEAR_2D(h=5, k=120, g=1, s=1, c=0) ABGR8888 0% 1% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 4% 0% 0% 0% 0% 0% 0% 0%
NVIDIA_BLOCK_LINEAR_2D(h=0, k=122, g=1, s=1, c=0) ABGR8888 0% 1% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 4% 0% 0% 0% 0% 0% 0% 0%
NVIDIA_BLOCK_LINEAR_2D(h=1, k=122, g=1, s=1, c=0) ABGR8888 0% 1% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 4% 0% 0% 0% 0% 0% 0% 0%
NVIDIA_BLOCK_LINEAR_2D(h=2, k=122, g=1, s=1, c=0) ABGR8888 0% 1% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 4% 0% 0% 0% 0% 0% 0% 0%
NVIDIA_BLOCK_LINEAR_2D(h=3, k=122, g=1, s=1, c=0) ABGR8888 0% 1% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 4% 0% 0% 0% 0% 0% 0% 0%
NVIDIA_BLOCK_LINEAR_2D(h=4, k=122, g=1, s=1, c=0) ABGR8888 0% 1% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 4% 0% 0% 0% 0% 0% 0% 0%
NVIDIA_BLOCK_LINEAR_2D(h=5, k=122, g=1, s=1, c=0) ABGR8888 0% 1% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 4% 0% 0% 0% 0% 0% 0% 0%
NVIDIA_BLOCK_LINEAR_2D(h=0, k=6, g=2, s=1, c=0) ABGR8888 16% 11% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 14% 85% 0% 0% 0% 0% 0% 0%
NVIDIA_BLOCK_LINEAR_2D(h=1, k=6, g=2, s=1, c=0) ABGR8888 16% 11% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 14% 85% 0% 0% 0% 0% 0% 0%
NVIDIA_BLOCK_LINEAR_2D(h=2, k=6, g=2, s=1, c=0) ABGR8888 16% 11% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 14% 85% 0% 0% 0% 0% 0% 0%
NVIDIA_BLOCK_LINEAR_2D(h=3, k=6, g=2, s=1, c=0) ABGR8888 16% 11% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 14% 85% 0% 0% 0% 0% 0% 0%
NVIDIA_BLOCK_LINEAR_2D(h=4, k=6, g=2, s=1, c=0) ABGR8888 16% 11% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 14% 85% 0% 0% 0% 0% 0% 0%
NVIDIA_BLOCK_LINEAR_2D(h=5, k=6, g=2, s=1, c=0) ABGR8888 16% 11% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 14% 85% 0% 0% 0% 0% 0% 0%
QCOM_COMPRESSED ABGR8888 2% 1% 22% 0% 0% 0% 0% 0% 0% 0% 0% 0% 67% 0% 0% 0% 0% 0% 0% 0% 0%
BROADCOM_VC4_T_TILED ABGR8888 3% 2% 33% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 100% 0%
ARM_AFBC(BLOCK_SIZE = 16x16) ABGR8888 1% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 100% 0% 0% 0% 0% 0%
ARM_AFBC(BLOCK_SIZE = 16x16, YTR) ABGR8888 1% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 100% 0% 0% 0% 0% 0%
ARM_AFBC(BLOCK_SIZE = 16x16, SPARSE) ABGR8888 1% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 100% 0% 0% 0% 0% 0%
ARM_AFBC(BLOCK_SIZE = 32x8, SPARSE) ABGR8888 0% 1% 0% 0% 0% 0% 0% 0% 0% 0% 0% 33% 0% 0% 0% 0% 0% 0% 0% 0% 0%
ARM_AFBC(BLOCK_SIZE = 16x16, YTR, SPARSE) ABGR8888 1% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 100% 0% 0% 0% 0% 0%
ARM_AFBC(BLOCK_SIZE = 32x8, YTR, SPARSE) ABGR8888 0% 1% 0% 0% 0% 0% 0% 0% 0% 0% 0% 33% 0% 0% 0% 0% 0% 0% 0% 0% 0%
ARM_AFBC(BLOCK_SIZE = 16x16, SPLIT, SPARSE) ABGR8888 0% 1% 0% 0% 0% 0% 0% 0% 0% 0% 0% 33% 0% 0% 0% 0% 0% 0% 0% 0% 0%
ARM_AFBC(BLOCK_SIZE = 32x8, SPLIT, SPARSE) ABGR8888 0% 1% 0% 0% 0% 0% 0% 0% 0% 0% 0% 33% 0% 0% 0% 0% 0% 0% 0% 0% 0%
ARM_AFBC(BLOCK_SIZE = 16x16, YTR, SPLIT, SPARSE) ABGR8888 1% 1% 0% 0% 0% 0% 0% 0% 0% 0% 0% 33% 0% 0% 0% 100% 0% 0% 0% 0% 0%
ARM_AFBC(BLOCK_SIZE = 32x8, YTR, SPLIT, SPARSE) ABGR8888 0% 1% 0% 0% 0% 0% 0% 0% 0% 0% 0% 33% 0% 0% 0% 0% 0% 0% 0% 0% 0%
ARM_AFBC(BLOCK_SIZE = 16x16, CBR) ABGR8888 1% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 100% 0% 0% 0% 0% 0%
ARM_AFBC(BLOCK_SIZE = 16x16, YTR, CBR) ABGR8888 1% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 100% 0% 0% 0% 0% 0%
ARM_AFBC(BLOCK_SIZE = 16x16, SPARSE, CBR) ABGR8888 1% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 100% 0% 0% 0% 0% 0%
ARM_AFBC(BLOCK_SIZE = 16x16, YTR, SPARSE, CBR) ABGR8888 1% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 100% 0% 0% 0% 0% 0%
unknown ABGR8888 1% 1% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 100% 0% 0% 0% 0%
unknown ABGR8888 1% 1% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 100% 0% 0% 0% 0%
unknown ABGR8888 1% 1% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 100% 0% 0% 0% 0%
unknown ABGR8888 1% 1% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 100% 0% 0% 0% 0%
unknown ABGR8888 1% 1% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 100% 0% 0% 0% 0%
unknown ABGR8888 1% 1% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 100% 0% 0% 0% 0%
unknown ABGR8888 1% 1% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 100% 0% 0% 0% 0%