DRM database formats

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Input formats

The percentages indicate the number of devices supporting the format and modifier. For instance, "50%" in the column for the "i915" driver would mean that half the known Intel devices support that format and modifier.

Modifier	Format	Planes		Drivers
		overlay	primary	meson
LINEAR	ABGR2101010	25%	25%	25%
LINEAR	YUV411	75%	0%	75%
LINEAR	NV21	100%	0%	100%
LINEAR	YUV420	75%	0%	75%
LINEAR	NV12	100%	0%	100%
LINEAR	BGRA8888	25%	25%	25%
LINEAR	RGBA8888	25%	25%	25%
LINEAR	ABGR8888	25%	100%	100%
LINEAR	XBGR8888	25%	100%	100%
LINEAR	BGR888	25%	25%	25%
LINEAR	RGB888	25%	100%	100%
LINEAR	ARGB8888	25%	100%	100%
LINEAR	XRGB8888	25%	100%	100%
LINEAR	VUY888	25%	0%	25%
LINEAR	YUV444	75%	0%	75%
LINEAR	BGRX8888	25%	25%	25%
LINEAR	RGBX8888	25%	25%	25%
LINEAR	RGB565	25%	100%	100%
LINEAR	YUV422	75%	0%	75%
LINEAR	YUV410	75%	0%	75%
LINEAR	YUYV	75%	0%	75%
LINEAR	UYVY	25%	0%	25%
ARM_AFBC(BLOCK_SIZE = 32x8, SPARSE)	ABGR8888	0%	25%	25%
ARM_AFBC(BLOCK_SIZE = 32x8, SPARSE)	XBGR8888	0%	25%	25%
ARM_AFBC(BLOCK_SIZE = 32x8, SPARSE)	RGB888	0%	25%	25%
ARM_AFBC(BLOCK_SIZE = 32x8, SPARSE)	ARGB8888	0%	25%	25%
ARM_AFBC(BLOCK_SIZE = 32x8, SPARSE)	XRGB8888	0%	25%	25%
ARM_AFBC(BLOCK_SIZE = 32x8, SPARSE)	RGB565	0%	25%	25%
ARM_AFBC(BLOCK_SIZE = 32x8, YTR, SPARSE)	ABGR8888	0%	25%	25%
ARM_AFBC(BLOCK_SIZE = 32x8, YTR, SPARSE)	XBGR8888	0%	25%	25%
ARM_AFBC(BLOCK_SIZE = 16x16, SPLIT, SPARSE)	ABGR2101010	25%	25%	25%
ARM_AFBC(BLOCK_SIZE = 16x16, SPLIT, SPARSE)	RGBA8888	25%	25%	25%
ARM_AFBC(BLOCK_SIZE = 16x16, SPLIT, SPARSE)	ABGR8888	25%	50%	50%
ARM_AFBC(BLOCK_SIZE = 16x16, SPLIT, SPARSE)	XBGR8888	25%	50%	50%
ARM_AFBC(BLOCK_SIZE = 16x16, SPLIT, SPARSE)	RGB888	25%	50%	50%
ARM_AFBC(BLOCK_SIZE = 16x16, SPLIT, SPARSE)	ARGB8888	25%	50%	50%
ARM_AFBC(BLOCK_SIZE = 16x16, SPLIT, SPARSE)	XRGB8888	25%	50%	50%
ARM_AFBC(BLOCK_SIZE = 16x16, SPLIT, SPARSE)	RGB565	25%	50%	50%
ARM_AFBC(BLOCK_SIZE = 32x8, SPLIT, SPARSE)	ABGR2101010	25%	25%	25%
ARM_AFBC(BLOCK_SIZE = 32x8, SPLIT, SPARSE)	RGBA8888	25%	25%	25%
ARM_AFBC(BLOCK_SIZE = 32x8, SPLIT, SPARSE)	ABGR8888	25%	50%	50%
ARM_AFBC(BLOCK_SIZE = 32x8, SPLIT, SPARSE)	XBGR8888	25%	50%	50%
ARM_AFBC(BLOCK_SIZE = 32x8, SPLIT, SPARSE)	RGB888	25%	50%	50%
ARM_AFBC(BLOCK_SIZE = 32x8, SPLIT, SPARSE)	ARGB8888	25%	50%	50%
ARM_AFBC(BLOCK_SIZE = 32x8, SPLIT, SPARSE)	XRGB8888	25%	50%	50%
ARM_AFBC(BLOCK_SIZE = 32x8, SPLIT, SPARSE)	RGB565	25%	50%	50%
ARM_AFBC(BLOCK_SIZE = 16x16, YTR, SPLIT, SPARSE)	ABGR2101010	25%	25%	25%
ARM_AFBC(BLOCK_SIZE = 16x16, YTR, SPLIT, SPARSE)	RGBA8888	25%	25%	25%
ARM_AFBC(BLOCK_SIZE = 16x16, YTR, SPLIT, SPARSE)	ABGR8888	25%	50%	50%
ARM_AFBC(BLOCK_SIZE = 16x16, YTR, SPLIT, SPARSE)	XBGR8888	25%	50%	50%
ARM_AFBC(BLOCK_SIZE = 16x16, YTR, SPLIT, SPARSE)	RGB888	25%	25%	25%
ARM_AFBC(BLOCK_SIZE = 32x8, YTR, SPLIT, SPARSE)	ABGR2101010	25%	25%	25%
ARM_AFBC(BLOCK_SIZE = 32x8, YTR, SPLIT, SPARSE)	RGBA8888	25%	25%	25%
ARM_AFBC(BLOCK_SIZE = 32x8, YTR, SPLIT, SPARSE)	ABGR8888	25%	50%	50%
ARM_AFBC(BLOCK_SIZE = 32x8, YTR, SPLIT, SPARSE)	XBGR8888	25%	50%	50%
ARM_AFBC(BLOCK_SIZE = 32x8, YTR, SPLIT, SPARSE)	RGB888	25%	25%	25%
ARM_AFBC(BLOCK_SIZE = 16x16, YTR, SPLIT, SPARSE, TILED, SC)	ABGR2101010	25%	25%	25%
ARM_AFBC(BLOCK_SIZE = 16x16, YTR, SPLIT, SPARSE, TILED, SC)	RGBA8888	25%	25%	25%
ARM_AFBC(BLOCK_SIZE = 16x16, YTR, SPLIT, SPARSE, TILED, SC)	ABGR8888	25%	25%	25%
ARM_AFBC(BLOCK_SIZE = 16x16, YTR, SPLIT, SPARSE, TILED, SC)	XBGR8888	25%	25%	25%
ARM_AFBC(BLOCK_SIZE = 16x16, YTR, SPLIT, SPARSE, TILED, SC)	RGB888	25%	25%	25%
ARM_AFBC(BLOCK_SIZE = 32x8, YTR, SPLIT, SPARSE, TILED, SC)	ABGR2101010	25%	25%	25%
ARM_AFBC(BLOCK_SIZE = 32x8, YTR, SPLIT, SPARSE, TILED, SC)	RGBA8888	25%	25%	25%
ARM_AFBC(BLOCK_SIZE = 32x8, YTR, SPLIT, SPARSE, TILED, SC)	ABGR8888	25%	25%	25%
ARM_AFBC(BLOCK_SIZE = 32x8, YTR, SPLIT, SPARSE, TILED, SC)	XBGR8888	25%	25%	25%
ARM_AFBC(BLOCK_SIZE = 32x8, YTR, SPLIT, SPARSE, TILED, SC)	RGB888	25%	25%	25%
ARM_AFRC(CU_SIZE_P0 = 16, LAYOUT = ROT)	ABGR2101010	25%	25%	25%
ARM_AFRC(CU_SIZE_P0 = 16, LAYOUT = ROT)	RGBA8888	25%	25%	25%
ARM_AFRC(CU_SIZE_P0 = 16, LAYOUT = ROT)	ABGR8888	25%	25%	25%
ARM_AFRC(CU_SIZE_P0 = 16, LAYOUT = ROT)	XBGR8888	25%	25%	25%
ARM_AFRC(CU_SIZE_P0 = 16, LAYOUT = ROT)	RGB888	25%	25%	25%
ARM_AFRC(CU_SIZE_P0 = 16, LAYOUT = ROT)	ARGB8888	25%	25%	25%
ARM_AFRC(CU_SIZE_P0 = 16, LAYOUT = ROT)	XRGB8888	25%	25%	25%
ARM_AFRC(CU_SIZE_P0 = 16, LAYOUT = ROT)	RGB565	25%	25%	25%
ARM_AFRC(CU_SIZE_P0 = 24, LAYOUT = ROT)	ABGR2101010	25%	25%	25%
ARM_AFRC(CU_SIZE_P0 = 24, LAYOUT = ROT)	RGBA8888	25%	25%	25%
ARM_AFRC(CU_SIZE_P0 = 24, LAYOUT = ROT)	ABGR8888	25%	25%	25%
ARM_AFRC(CU_SIZE_P0 = 24, LAYOUT = ROT)	XBGR8888	25%	25%	25%
ARM_AFRC(CU_SIZE_P0 = 24, LAYOUT = ROT)	RGB888	25%	25%	25%
ARM_AFRC(CU_SIZE_P0 = 24, LAYOUT = ROT)	ARGB8888	25%	25%	25%
ARM_AFRC(CU_SIZE_P0 = 24, LAYOUT = ROT)	XRGB8888	25%	25%	25%
ARM_AFRC(CU_SIZE_P0 = 24, LAYOUT = ROT)	RGB565	25%	25%	25%
ARM_AFRC(CU_SIZE_P0 = 32, LAYOUT = ROT)	ABGR2101010	25%	25%	25%
ARM_AFRC(CU_SIZE_P0 = 32, LAYOUT = ROT)	RGBA8888	25%	25%	25%
ARM_AFRC(CU_SIZE_P0 = 32, LAYOUT = ROT)	ABGR8888	25%	25%	25%
ARM_AFRC(CU_SIZE_P0 = 32, LAYOUT = ROT)	XBGR8888	25%	25%	25%
ARM_AFRC(CU_SIZE_P0 = 32, LAYOUT = ROT)	RGB888	25%	25%	25%
ARM_AFRC(CU_SIZE_P0 = 32, LAYOUT = ROT)	ARGB8888	25%	25%	25%
ARM_AFRC(CU_SIZE_P0 = 32, LAYOUT = ROT)	XRGB8888	25%	25%	25%
ARM_AFRC(CU_SIZE_P0 = 32, LAYOUT = ROT)	RGB565	25%	25%	25%
AMLOGIC_FBC(layout = BASIC, options = 0)	YUV420_10BIT	75%	0%	75%
AMLOGIC_FBC(layout = BASIC, options = 0)	YUV420_8BIT	75%	0%	75%
AMLOGIC_FBC(layout = SCATTER, options = 0)	YUV420_10BIT	75%	0%	75%
AMLOGIC_FBC(layout = SCATTER, options = 0)	YUV420_8BIT	75%	0%	75%
AMLOGIC_FBC(layout = BASIC, options = MEM_SAVING)	YUV420_10BIT	75%	0%	75%
AMLOGIC_FBC(layout = BASIC, options = MEM_SAVING)	YUV420_8BIT	75%	0%	75%
AMLOGIC_FBC(layout = SCATTER, options = MEM_SAVING)	YUV420_10BIT	75%	0%	75%
AMLOGIC_FBC(layout = SCATTER, options = MEM_SAVING)	YUV420_8BIT	75%	0%	75%