DRM database formats

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Filters: ARM_AFBC(BLOCK_SIZE = 32x8, YTR, SPLIT, SPARSE) ×

Input formats

The percentages indicate the number of devices supporting the format and modifier. For instance, "50%" in the column for the "i915" driver would mean that half the known Intel devices support that format and modifier.

Modifier Format Planes Drivers
overlay primary meson sunxi-drm
ARM_AFBC(BLOCK_SIZE = 32x8, YTR, SPLIT, SPARSE) YUV411 100% 0% 0% 100%
ARM_AFBC(BLOCK_SIZE = 32x8, YTR, SPLIT, SPARSE) NV21 100% 0% 0% 100%
ARM_AFBC(BLOCK_SIZE = 32x8, YTR, SPLIT, SPARSE) NV61 100% 0% 0% 100%
ARM_AFBC(BLOCK_SIZE = 32x8, YTR, SPLIT, SPARSE) BGRA4444 100% 50% 0% 100%
ARM_AFBC(BLOCK_SIZE = 32x8, YTR, SPLIT, SPARSE) RGBA4444 100% 50% 0% 100%
ARM_AFBC(BLOCK_SIZE = 32x8, YTR, SPLIT, SPARSE) ABGR4444 100% 50% 0% 100%
ARM_AFBC(BLOCK_SIZE = 32x8, YTR, SPLIT, SPARSE) ARGB4444 100% 50% 0% 100%
ARM_AFBC(BLOCK_SIZE = 32x8, YTR, SPLIT, SPARSE) YUV420 100% 0% 0% 100%
ARM_AFBC(BLOCK_SIZE = 32x8, YTR, SPLIT, SPARSE) NV12 100% 0% 0% 100%
ARM_AFBC(BLOCK_SIZE = 32x8, YTR, SPLIT, SPARSE) YVU420 100% 0% 0% 100%
ARM_AFBC(BLOCK_SIZE = 32x8, YTR, SPLIT, SPARSE) BGRA8888 100% 50% 0% 100%
ARM_AFBC(BLOCK_SIZE = 32x8, YTR, SPLIT, SPARSE) RGBA8888 100% 50% 0% 100%
ARM_AFBC(BLOCK_SIZE = 32x8, YTR, SPLIT, SPARSE) ABGR8888 100% 100% 100% 100%
ARM_AFBC(BLOCK_SIZE = 32x8, YTR, SPLIT, SPARSE) XBGR8888 100% 100% 100% 100%
ARM_AFBC(BLOCK_SIZE = 32x8, YTR, SPLIT, SPARSE) BGR888 100% 50% 0% 100%
ARM_AFBC(BLOCK_SIZE = 32x8, YTR, SPLIT, SPARSE) RGB888 100% 50% 0% 100%
ARM_AFBC(BLOCK_SIZE = 32x8, YTR, SPLIT, SPARSE) ARGB8888 100% 50% 0% 100%
ARM_AFBC(BLOCK_SIZE = 32x8, YTR, SPLIT, SPARSE) XRGB8888 100% 50% 0% 100%
ARM_AFBC(BLOCK_SIZE = 32x8, YTR, SPLIT, SPARSE) YUV444 100% 0% 0% 100%
ARM_AFBC(BLOCK_SIZE = 32x8, YTR, SPLIT, SPARSE) BGRX8888 100% 50% 0% 100%
ARM_AFBC(BLOCK_SIZE = 32x8, YTR, SPLIT, SPARSE) RGBX8888 100% 50% 0% 100%
ARM_AFBC(BLOCK_SIZE = 32x8, YTR, SPLIT, SPARSE) BGRA5551 100% 50% 0% 100%
ARM_AFBC(BLOCK_SIZE = 32x8, YTR, SPLIT, SPARSE) RGBA5551 100% 50% 0% 100%
ARM_AFBC(BLOCK_SIZE = 32x8, YTR, SPLIT, SPARSE) ABGR1555 100% 50% 0% 100%
ARM_AFBC(BLOCK_SIZE = 32x8, YTR, SPLIT, SPARSE) ARGB1555 100% 50% 0% 100%
ARM_AFBC(BLOCK_SIZE = 32x8, YTR, SPLIT, SPARSE) BGR565 100% 50% 0% 100%
ARM_AFBC(BLOCK_SIZE = 32x8, YTR, SPLIT, SPARSE) RGB565 100% 50% 0% 100%
ARM_AFBC(BLOCK_SIZE = 32x8, YTR, SPLIT, SPARSE) YUV422 100% 0% 0% 100%
ARM_AFBC(BLOCK_SIZE = 32x8, YTR, SPLIT, SPARSE) NV16 100% 0% 0% 100%
ARM_AFBC(BLOCK_SIZE = 32x8, YTR, SPLIT, SPARSE) AYUV 100% 0% 0% 100%