DRM database formats

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Filters: sunxi-drm ×

Input formats

The percentages indicate the number of devices supporting the format and modifier. For instance, "50%" in the column for the "i915" driver would mean that half the known Intel devices support that format and modifier.

Modifier	Format	Planes		Drivers
		overlay	primary	sunxi-drm
LINEAR	YUV411	100%	0%	100%
LINEAR	NV21	100%	0%	100%
LINEAR	NV61	100%	0%	100%
LINEAR	BGRA4444	100%	100%	100%
LINEAR	RGBA4444	100%	100%	100%
LINEAR	ABGR4444	100%	100%	100%
LINEAR	ARGB4444	100%	100%	100%
LINEAR	YUV420	100%	0%	100%
LINEAR	NV12	100%	0%	100%
LINEAR	YVU420	100%	0%	100%
LINEAR	BGRA8888	100%	100%	100%
LINEAR	RGBA8888	100%	100%	100%
LINEAR	ABGR8888	100%	100%	100%
LINEAR	XBGR8888	100%	100%	100%
LINEAR	BGR888	100%	100%	100%
LINEAR	RGB888	100%	100%	100%
LINEAR	ARGB8888	100%	100%	100%
LINEAR	XRGB8888	100%	100%	100%
LINEAR	YUV444	100%	0%	100%
LINEAR	BGRX8888	100%	100%	100%
LINEAR	RGBX8888	100%	100%	100%
LINEAR	BGRA5551	100%	100%	100%
LINEAR	RGBA5551	100%	100%	100%
LINEAR	ABGR1555	100%	100%	100%
LINEAR	ARGB1555	100%	100%	100%
LINEAR	BGR565	100%	100%	100%
LINEAR	RGB565	100%	100%	100%
LINEAR	YUV422	100%	0%	100%
LINEAR	NV16	100%	0%	100%
LINEAR	AYUV	100%	0%	100%
ARM_AFBC(BLOCK_SIZE = 16x16, SPLIT, SPARSE)	YUV411	100%	0%	100%
ARM_AFBC(BLOCK_SIZE = 16x16, SPLIT, SPARSE)	NV21	100%	0%	100%
ARM_AFBC(BLOCK_SIZE = 16x16, SPLIT, SPARSE)	NV61	100%	0%	100%
ARM_AFBC(BLOCK_SIZE = 16x16, SPLIT, SPARSE)	BGRA4444	100%	100%	100%
ARM_AFBC(BLOCK_SIZE = 16x16, SPLIT, SPARSE)	RGBA4444	100%	100%	100%
ARM_AFBC(BLOCK_SIZE = 16x16, SPLIT, SPARSE)	ABGR4444	100%	100%	100%
ARM_AFBC(BLOCK_SIZE = 16x16, SPLIT, SPARSE)	ARGB4444	100%	100%	100%
ARM_AFBC(BLOCK_SIZE = 16x16, SPLIT, SPARSE)	YUV420	100%	0%	100%
ARM_AFBC(BLOCK_SIZE = 16x16, SPLIT, SPARSE)	NV12	100%	0%	100%
ARM_AFBC(BLOCK_SIZE = 16x16, SPLIT, SPARSE)	YVU420	100%	0%	100%
ARM_AFBC(BLOCK_SIZE = 16x16, SPLIT, SPARSE)	BGRA8888	100%	100%	100%
ARM_AFBC(BLOCK_SIZE = 16x16, SPLIT, SPARSE)	RGBA8888	100%	100%	100%
ARM_AFBC(BLOCK_SIZE = 16x16, SPLIT, SPARSE)	ABGR8888	100%	100%	100%
ARM_AFBC(BLOCK_SIZE = 16x16, SPLIT, SPARSE)	XBGR8888	100%	100%	100%
ARM_AFBC(BLOCK_SIZE = 16x16, SPLIT, SPARSE)	BGR888	100%	100%	100%
ARM_AFBC(BLOCK_SIZE = 16x16, SPLIT, SPARSE)	RGB888	100%	100%	100%
ARM_AFBC(BLOCK_SIZE = 16x16, SPLIT, SPARSE)	ARGB8888	100%	100%	100%
ARM_AFBC(BLOCK_SIZE = 16x16, SPLIT, SPARSE)	XRGB8888	100%	100%	100%
ARM_AFBC(BLOCK_SIZE = 16x16, SPLIT, SPARSE)	YUV444	100%	0%	100%
ARM_AFBC(BLOCK_SIZE = 16x16, SPLIT, SPARSE)	BGRX8888	100%	100%	100%
ARM_AFBC(BLOCK_SIZE = 16x16, SPLIT, SPARSE)	RGBX8888	100%	100%	100%
ARM_AFBC(BLOCK_SIZE = 16x16, SPLIT, SPARSE)	BGRA5551	100%	100%	100%
ARM_AFBC(BLOCK_SIZE = 16x16, SPLIT, SPARSE)	RGBA5551	100%	100%	100%
ARM_AFBC(BLOCK_SIZE = 16x16, SPLIT, SPARSE)	ABGR1555	100%	100%	100%
ARM_AFBC(BLOCK_SIZE = 16x16, SPLIT, SPARSE)	ARGB1555	100%	100%	100%
ARM_AFBC(BLOCK_SIZE = 16x16, SPLIT, SPARSE)	BGR565	100%	100%	100%
ARM_AFBC(BLOCK_SIZE = 16x16, SPLIT, SPARSE)	RGB565	100%	100%	100%
ARM_AFBC(BLOCK_SIZE = 16x16, SPLIT, SPARSE)	YUV422	100%	0%	100%
ARM_AFBC(BLOCK_SIZE = 16x16, SPLIT, SPARSE)	NV16	100%	0%	100%
ARM_AFBC(BLOCK_SIZE = 16x16, SPLIT, SPARSE)	AYUV	100%	0%	100%
ARM_AFBC(BLOCK_SIZE = 32x8, YTR, SPLIT, SPARSE)	YUV411	100%	0%	100%
ARM_AFBC(BLOCK_SIZE = 32x8, YTR, SPLIT, SPARSE)	NV21	100%	0%	100%
ARM_AFBC(BLOCK_SIZE = 32x8, YTR, SPLIT, SPARSE)	NV61	100%	0%	100%
ARM_AFBC(BLOCK_SIZE = 32x8, YTR, SPLIT, SPARSE)	BGRA4444	100%	100%	100%
ARM_AFBC(BLOCK_SIZE = 32x8, YTR, SPLIT, SPARSE)	RGBA4444	100%	100%	100%
ARM_AFBC(BLOCK_SIZE = 32x8, YTR, SPLIT, SPARSE)	ABGR4444	100%	100%	100%
ARM_AFBC(BLOCK_SIZE = 32x8, YTR, SPLIT, SPARSE)	ARGB4444	100%	100%	100%
ARM_AFBC(BLOCK_SIZE = 32x8, YTR, SPLIT, SPARSE)	YUV420	100%	0%	100%
ARM_AFBC(BLOCK_SIZE = 32x8, YTR, SPLIT, SPARSE)	NV12	100%	0%	100%
ARM_AFBC(BLOCK_SIZE = 32x8, YTR, SPLIT, SPARSE)	YVU420	100%	0%	100%
ARM_AFBC(BLOCK_SIZE = 32x8, YTR, SPLIT, SPARSE)	BGRA8888	100%	100%	100%
ARM_AFBC(BLOCK_SIZE = 32x8, YTR, SPLIT, SPARSE)	RGBA8888	100%	100%	100%
ARM_AFBC(BLOCK_SIZE = 32x8, YTR, SPLIT, SPARSE)	ABGR8888	100%	100%	100%
ARM_AFBC(BLOCK_SIZE = 32x8, YTR, SPLIT, SPARSE)	XBGR8888	100%	100%	100%
ARM_AFBC(BLOCK_SIZE = 32x8, YTR, SPLIT, SPARSE)	BGR888	100%	100%	100%
ARM_AFBC(BLOCK_SIZE = 32x8, YTR, SPLIT, SPARSE)	RGB888	100%	100%	100%
ARM_AFBC(BLOCK_SIZE = 32x8, YTR, SPLIT, SPARSE)	ARGB8888	100%	100%	100%
ARM_AFBC(BLOCK_SIZE = 32x8, YTR, SPLIT, SPARSE)	XRGB8888	100%	100%	100%
ARM_AFBC(BLOCK_SIZE = 32x8, YTR, SPLIT, SPARSE)	YUV444	100%	0%	100%
ARM_AFBC(BLOCK_SIZE = 32x8, YTR, SPLIT, SPARSE)	BGRX8888	100%	100%	100%
ARM_AFBC(BLOCK_SIZE = 32x8, YTR, SPLIT, SPARSE)	RGBX8888	100%	100%	100%
ARM_AFBC(BLOCK_SIZE = 32x8, YTR, SPLIT, SPARSE)	BGRA5551	100%	100%	100%
ARM_AFBC(BLOCK_SIZE = 32x8, YTR, SPLIT, SPARSE)	RGBA5551	100%	100%	100%
ARM_AFBC(BLOCK_SIZE = 32x8, YTR, SPLIT, SPARSE)	ABGR1555	100%	100%	100%
ARM_AFBC(BLOCK_SIZE = 32x8, YTR, SPLIT, SPARSE)	ARGB1555	100%	100%	100%
ARM_AFBC(BLOCK_SIZE = 32x8, YTR, SPLIT, SPARSE)	BGR565	100%	100%	100%
ARM_AFBC(BLOCK_SIZE = 32x8, YTR, SPLIT, SPARSE)	RGB565	100%	100%	100%
ARM_AFBC(BLOCK_SIZE = 32x8, YTR, SPLIT, SPARSE)	YUV422	100%	0%	100%
ARM_AFBC(BLOCK_SIZE = 32x8, YTR, SPLIT, SPARSE)	NV16	100%	0%	100%
ARM_AFBC(BLOCK_SIZE = 32x8, YTR, SPLIT, SPARSE)	AYUV	100%	0%	100%