Filters: BGR565 ×
The percentages indicate the number of devices supporting the format and modifier. For instance, "50%" in the column for the "i915" driver would mean that half the known Intel devices support that format and modifier.
Modifier | Format | Planes | Drivers | ||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
overlay | primary | cursor | kirin | mga2 | msm | rockchip | smifb | spacemit | starfive | sun4i-drm | sunxi-drm | tegra | vc4 | vs-drm | xlnx | ||
LINEAR | BGR565 | 100% | 100% | 100% | 100% | 100% | 100% | 100% | 100% | 100% | 100% | 100% | 100% | 100% | 100% | 100% | 100% |
NVIDIA_BLOCK_LINEAR_2D(h=0, k=0, g=0, s=0, c=0) | BGR565 | 0% | 5% | 0% | 0% | 0% | 0% | 0% | 0% | 0% | 0% | 0% | 0% | 100% | 0% | 0% | 0% |
NVIDIA_BLOCK_LINEAR_2D(h=1, k=0, g=0, s=0, c=0) | BGR565 | 0% | 5% | 0% | 0% | 0% | 0% | 0% | 0% | 0% | 0% | 0% | 0% | 100% | 0% | 0% | 0% |
NVIDIA_BLOCK_LINEAR_2D(h=2, k=0, g=0, s=0, c=0) | BGR565 | 0% | 5% | 0% | 0% | 0% | 0% | 0% | 0% | 0% | 0% | 0% | 0% | 100% | 0% | 0% | 0% |
NVIDIA_BLOCK_LINEAR_2D(h=3, k=0, g=0, s=0, c=0) | BGR565 | 0% | 5% | 0% | 0% | 0% | 0% | 0% | 0% | 0% | 0% | 0% | 0% | 100% | 0% | 0% | 0% |
NVIDIA_BLOCK_LINEAR_2D(h=4, k=0, g=0, s=0, c=0) | BGR565 | 0% | 5% | 0% | 0% | 0% | 0% | 0% | 0% | 0% | 0% | 0% | 0% | 100% | 0% | 0% | 0% |
NVIDIA_BLOCK_LINEAR_2D(h=5, k=0, g=0, s=0, c=0) | BGR565 | 0% | 5% | 0% | 0% | 0% | 0% | 0% | 0% | 0% | 0% | 0% | 0% | 100% | 0% | 0% | 0% |
QCOM_COMPRESSED | BGR565 | 12% | 10% | 22% | 0% | 0% | 67% | 0% | 0% | 0% | 0% | 0% | 0% | 0% | 0% | 0% | 0% |
BROADCOM_VC4_T_TILED | BGR565 | 19% | 14% | 33% | 0% | 0% | 0% | 0% | 0% | 0% | 0% | 0% | 0% | 0% | 100% | 0% | 0% |
ARM_AFBC(BLOCK_SIZE = 16x16) | BGR565 | 6% | 5% | 0% | 0% | 0% | 0% | 100% | 0% | 0% | 0% | 0% | 0% | 0% | 0% | 0% | 0% |
ARM_AFBC(BLOCK_SIZE = 16x16, YTR) | BGR565 | 6% | 5% | 0% | 0% | 0% | 0% | 100% | 0% | 0% | 0% | 0% | 0% | 0% | 0% | 0% | 0% |
ARM_AFBC(BLOCK_SIZE = 16x16, SPARSE) | BGR565 | 6% | 5% | 0% | 0% | 0% | 0% | 100% | 0% | 0% | 0% | 0% | 0% | 0% | 0% | 0% | 0% |
ARM_AFBC(BLOCK_SIZE = 16x16, YTR, SPARSE) | BGR565 | 6% | 5% | 0% | 0% | 0% | 0% | 100% | 0% | 0% | 0% | 0% | 0% | 0% | 0% | 0% | 0% |
ARM_AFBC(BLOCK_SIZE = 16x16, SPLIT, SPARSE) | BGR565 | 6% | 5% | 0% | 0% | 0% | 0% | 0% | 0% | 0% | 0% | 0% | 100% | 0% | 0% | 0% | 0% |
ARM_AFBC(BLOCK_SIZE = 16x16, YTR, SPLIT, SPARSE) | BGR565 | 6% | 5% | 0% | 0% | 0% | 0% | 100% | 0% | 0% | 0% | 0% | 0% | 0% | 0% | 0% | 0% |
ARM_AFBC(BLOCK_SIZE = 32x8, YTR, SPLIT, SPARSE) | BGR565 | 6% | 5% | 0% | 0% | 0% | 0% | 0% | 0% | 0% | 0% | 0% | 100% | 0% | 0% | 0% | 0% |
ARM_AFBC(BLOCK_SIZE = 16x16, CBR) | BGR565 | 6% | 5% | 0% | 0% | 0% | 0% | 100% | 0% | 0% | 0% | 0% | 0% | 0% | 0% | 0% | 0% |
ARM_AFBC(BLOCK_SIZE = 16x16, YTR, CBR) | BGR565 | 6% | 5% | 0% | 0% | 0% | 0% | 100% | 0% | 0% | 0% | 0% | 0% | 0% | 0% | 0% | 0% |
ARM_AFBC(BLOCK_SIZE = 16x16, SPARSE, CBR) | BGR565 | 6% | 5% | 0% | 0% | 0% | 0% | 100% | 0% | 0% | 0% | 0% | 0% | 0% | 0% | 0% | 0% |
ARM_AFBC(BLOCK_SIZE = 16x16, YTR, SPARSE, CBR) | BGR565 | 6% | 5% | 0% | 0% | 0% | 0% | 100% | 0% | 0% | 0% | 0% | 0% | 0% | 0% | 0% | 0% |
unknown | BGR565 | 12% | 10% | 0% | 0% | 0% | 0% | 0% | 0% | 0% | 100% | 0% | 0% | 0% | 0% | 100% | 0% |
unknown | BGR565 | 12% | 10% | 0% | 0% | 0% | 0% | 0% | 0% | 0% | 100% | 0% | 0% | 0% | 0% | 100% | 0% |
unknown | BGR565 | 12% | 10% | 0% | 0% | 0% | 0% | 0% | 0% | 0% | 100% | 0% | 0% | 0% | 0% | 100% | 0% |
unknown | BGR565 | 12% | 10% | 0% | 0% | 0% | 0% | 0% | 0% | 0% | 100% | 0% | 0% | 0% | 0% | 100% | 0% |
unknown | BGR565 | 12% | 10% | 0% | 0% | 0% | 0% | 0% | 0% | 0% | 100% | 0% | 0% | 0% | 0% | 100% | 0% |
unknown | BGR565 | 12% | 10% | 0% | 0% | 0% | 0% | 0% | 0% | 0% | 100% | 0% | 0% | 0% | 0% | 100% | 0% |
unknown | BGR565 | 12% | 10% | 0% | 0% | 0% | 0% | 0% | 0% | 0% | 100% | 0% | 0% | 0% | 0% | 100% | 0% |