DRM database formats

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Filters: rockchip ×

Input formats

The percentages indicate the number of devices supporting the format and modifier. For instance, "50%" in the column for the "i915" driver would mean that half the known Intel devices support that format and modifier.

Modifier Format Planes Drivers
overlay primary rockchip
linear NV12 100% 0% 100%
linear ABGR8888 100% 100% 100%
linear XBGR8888 100% 100% 100%
linear BGR888 100% 100% 100%
linear RGB888 100% 100% 100%
linear ARGB8888 100% 100% 100%
linear XRGB8888 100% 100% 100%
linear NV24 100% 0% 100%
linear BGR565 100% 100% 100%
linear RGB565 100% 100% 100%
linear NV16 100% 0% 100%
linear YVYU 100% 0% 100%
linear VYUY 100% 0% 100%
ARM_AFBC(BLOCK_SIZE = 16x16) NV12 100% 0% 100%
ARM_AFBC(BLOCK_SIZE = 16x16) ABGR8888 100% 0% 100%
ARM_AFBC(BLOCK_SIZE = 16x16) XBGR8888 100% 0% 100%
ARM_AFBC(BLOCK_SIZE = 16x16) BGR888 100% 0% 100%
ARM_AFBC(BLOCK_SIZE = 16x16) RGB888 100% 0% 100%
ARM_AFBC(BLOCK_SIZE = 16x16) ARGB8888 100% 0% 100%
ARM_AFBC(BLOCK_SIZE = 16x16) XRGB8888 100% 0% 100%
ARM_AFBC(BLOCK_SIZE = 16x16) BGR565 100% 0% 100%
ARM_AFBC(BLOCK_SIZE = 16x16) RGB565 100% 0% 100%
ARM_AFBC(BLOCK_SIZE = 16x16) NV16 100% 0% 100%
ARM_AFBC(BLOCK_SIZE = 16x16, YTR) NV12 100% 0% 100%
ARM_AFBC(BLOCK_SIZE = 16x16, YTR) ABGR8888 100% 0% 100%
ARM_AFBC(BLOCK_SIZE = 16x16, YTR) XBGR8888 100% 0% 100%
ARM_AFBC(BLOCK_SIZE = 16x16, YTR) BGR888 100% 0% 100%
ARM_AFBC(BLOCK_SIZE = 16x16, YTR) RGB888 100% 0% 100%
ARM_AFBC(BLOCK_SIZE = 16x16, YTR) ARGB8888 100% 0% 100%
ARM_AFBC(BLOCK_SIZE = 16x16, YTR) XRGB8888 100% 0% 100%
ARM_AFBC(BLOCK_SIZE = 16x16, YTR) BGR565 100% 0% 100%
ARM_AFBC(BLOCK_SIZE = 16x16, YTR) RGB565 100% 0% 100%
ARM_AFBC(BLOCK_SIZE = 16x16, YTR) NV16 100% 0% 100%
ARM_AFBC(BLOCK_SIZE = 16x16, SPARSE) NV12 100% 0% 100%
ARM_AFBC(BLOCK_SIZE = 16x16, SPARSE) ABGR8888 100% 0% 100%
ARM_AFBC(BLOCK_SIZE = 16x16, SPARSE) XBGR8888 100% 0% 100%
ARM_AFBC(BLOCK_SIZE = 16x16, SPARSE) BGR888 100% 0% 100%
ARM_AFBC(BLOCK_SIZE = 16x16, SPARSE) RGB888 100% 0% 100%
ARM_AFBC(BLOCK_SIZE = 16x16, SPARSE) ARGB8888 100% 0% 100%
ARM_AFBC(BLOCK_SIZE = 16x16, SPARSE) XRGB8888 100% 0% 100%
ARM_AFBC(BLOCK_SIZE = 16x16, SPARSE) BGR565 100% 0% 100%
ARM_AFBC(BLOCK_SIZE = 16x16, SPARSE) RGB565 100% 0% 100%
ARM_AFBC(BLOCK_SIZE = 16x16, SPARSE) NV16 100% 0% 100%
ARM_AFBC(BLOCK_SIZE = 16x16, YTR, SPARSE) NV12 100% 0% 100%
ARM_AFBC(BLOCK_SIZE = 16x16, YTR, SPARSE) ABGR8888 100% 0% 100%
ARM_AFBC(BLOCK_SIZE = 16x16, YTR, SPARSE) XBGR8888 100% 0% 100%
ARM_AFBC(BLOCK_SIZE = 16x16, YTR, SPARSE) BGR888 100% 0% 100%
ARM_AFBC(BLOCK_SIZE = 16x16, YTR, SPARSE) RGB888 100% 0% 100%
ARM_AFBC(BLOCK_SIZE = 16x16, YTR, SPARSE) ARGB8888 100% 0% 100%
ARM_AFBC(BLOCK_SIZE = 16x16, YTR, SPARSE) XRGB8888 100% 0% 100%
ARM_AFBC(BLOCK_SIZE = 16x16, YTR, SPARSE) BGR565 100% 0% 100%
ARM_AFBC(BLOCK_SIZE = 16x16, YTR, SPARSE) RGB565 100% 0% 100%
ARM_AFBC(BLOCK_SIZE = 16x16, YTR, SPARSE) NV16 100% 0% 100%
ARM_AFBC(BLOCK_SIZE = 16x16, YTR, SPLIT, SPARSE) NV12 100% 0% 100%
ARM_AFBC(BLOCK_SIZE = 16x16, YTR, SPLIT, SPARSE) ABGR8888 100% 0% 100%
ARM_AFBC(BLOCK_SIZE = 16x16, YTR, SPLIT, SPARSE) XBGR8888 100% 0% 100%
ARM_AFBC(BLOCK_SIZE = 16x16, YTR, SPLIT, SPARSE) BGR888 100% 0% 100%
ARM_AFBC(BLOCK_SIZE = 16x16, YTR, SPLIT, SPARSE) RGB888 100% 0% 100%
ARM_AFBC(BLOCK_SIZE = 16x16, YTR, SPLIT, SPARSE) ARGB8888 100% 0% 100%
ARM_AFBC(BLOCK_SIZE = 16x16, YTR, SPLIT, SPARSE) XRGB8888 100% 0% 100%
ARM_AFBC(BLOCK_SIZE = 16x16, YTR, SPLIT, SPARSE) BGR565 100% 0% 100%
ARM_AFBC(BLOCK_SIZE = 16x16, YTR, SPLIT, SPARSE) RGB565 100% 0% 100%
ARM_AFBC(BLOCK_SIZE = 16x16, YTR, SPLIT, SPARSE) NV16 100% 0% 100%
ARM_AFBC(BLOCK_SIZE = 16x16, CBR) NV12 100% 0% 100%
ARM_AFBC(BLOCK_SIZE = 16x16, CBR) ABGR8888 100% 0% 100%
ARM_AFBC(BLOCK_SIZE = 16x16, CBR) XBGR8888 100% 0% 100%
ARM_AFBC(BLOCK_SIZE = 16x16, CBR) BGR888 100% 0% 100%
ARM_AFBC(BLOCK_SIZE = 16x16, CBR) RGB888 100% 0% 100%
ARM_AFBC(BLOCK_SIZE = 16x16, CBR) ARGB8888 100% 0% 100%
ARM_AFBC(BLOCK_SIZE = 16x16, CBR) XRGB8888 100% 0% 100%
ARM_AFBC(BLOCK_SIZE = 16x16, CBR) BGR565 100% 0% 100%
ARM_AFBC(BLOCK_SIZE = 16x16, CBR) RGB565 100% 0% 100%
ARM_AFBC(BLOCK_SIZE = 16x16, CBR) NV16 100% 0% 100%
ARM_AFBC(BLOCK_SIZE = 16x16, YTR, CBR) NV12 100% 0% 100%
ARM_AFBC(BLOCK_SIZE = 16x16, YTR, CBR) ABGR8888 100% 0% 100%
ARM_AFBC(BLOCK_SIZE = 16x16, YTR, CBR) XBGR8888 100% 0% 100%
ARM_AFBC(BLOCK_SIZE = 16x16, YTR, CBR) BGR888 100% 0% 100%
ARM_AFBC(BLOCK_SIZE = 16x16, YTR, CBR) RGB888 100% 0% 100%
ARM_AFBC(BLOCK_SIZE = 16x16, YTR, CBR) ARGB8888 100% 0% 100%
ARM_AFBC(BLOCK_SIZE = 16x16, YTR, CBR) XRGB8888 100% 0% 100%
ARM_AFBC(BLOCK_SIZE = 16x16, YTR, CBR) BGR565 100% 0% 100%
ARM_AFBC(BLOCK_SIZE = 16x16, YTR, CBR) RGB565 100% 0% 100%
ARM_AFBC(BLOCK_SIZE = 16x16, YTR, CBR) NV16 100% 0% 100%
ARM_AFBC(BLOCK_SIZE = 16x16, SPARSE, CBR) NV12 100% 0% 100%
ARM_AFBC(BLOCK_SIZE = 16x16, SPARSE, CBR) ABGR8888 100% 0% 100%
ARM_AFBC(BLOCK_SIZE = 16x16, SPARSE, CBR) XBGR8888 100% 0% 100%
ARM_AFBC(BLOCK_SIZE = 16x16, SPARSE, CBR) BGR888 100% 0% 100%
ARM_AFBC(BLOCK_SIZE = 16x16, SPARSE, CBR) RGB888 100% 0% 100%
ARM_AFBC(BLOCK_SIZE = 16x16, SPARSE, CBR) ARGB8888 100% 0% 100%
ARM_AFBC(BLOCK_SIZE = 16x16, SPARSE, CBR) XRGB8888 100% 0% 100%
ARM_AFBC(BLOCK_SIZE = 16x16, SPARSE, CBR) BGR565 100% 0% 100%
ARM_AFBC(BLOCK_SIZE = 16x16, SPARSE, CBR) RGB565 100% 0% 100%
ARM_AFBC(BLOCK_SIZE = 16x16, SPARSE, CBR) NV16 100% 0% 100%
ARM_AFBC(BLOCK_SIZE = 16x16, YTR, SPARSE, CBR) NV12 100% 0% 100%
ARM_AFBC(BLOCK_SIZE = 16x16, YTR, SPARSE, CBR) ABGR8888 100% 0% 100%
ARM_AFBC(BLOCK_SIZE = 16x16, YTR, SPARSE, CBR) XBGR8888 100% 0% 100%
ARM_AFBC(BLOCK_SIZE = 16x16, YTR, SPARSE, CBR) BGR888 100% 0% 100%
ARM_AFBC(BLOCK_SIZE = 16x16, YTR, SPARSE, CBR) RGB888 100% 0% 100%
ARM_AFBC(BLOCK_SIZE = 16x16, YTR, SPARSE, CBR) ARGB8888 100% 0% 100%
ARM_AFBC(BLOCK_SIZE = 16x16, YTR, SPARSE, CBR) XRGB8888 100% 0% 100%
ARM_AFBC(BLOCK_SIZE = 16x16, YTR, SPARSE, CBR) BGR565 100% 0% 100%
ARM_AFBC(BLOCK_SIZE = 16x16, YTR, SPARSE, CBR) RGB565 100% 0% 100%
ARM_AFBC(BLOCK_SIZE = 16x16, YTR, SPARSE, CBR) NV16 100% 0% 100%