DRM database formats

Back to index

Filters: XRGB16161616 ×

Input formats

The percentages indicate the number of devices supporting the format and modifier. For instance, "50%" in the column for the "i915" driver would mean that half the known Intel devices support that format and modifier.

Modifier Format Planes Drivers
overlay primary cursor amdgpu vkms
LINEAR XRGB16161616 100% 100% 100% 100% 100%
AMD(TILE_VERSION = unknown, TILE = unknown) XRGB16161616 4% 2% 0% 2% 0%
AMD(TILE_VERSION = unknown, TILE = unknown) XRGB16161616 4% 2% 0% 2% 0%
AMD(TILE_VERSION = unknown, TILE = unknown) XRGB16161616 4% 2% 0% 2% 0%
AMD(TILE_VERSION = unknown, TILE = unknown) XRGB16161616 4% 2% 0% 2% 0%
AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_S) XRGB16161616 62% 43% 0% 44% 0%
AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_D) XRGB16161616 62% 45% 0% 47% 0%
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_D) XRGB16161616 31% 17% 0% 18% 0%
AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 64B) XRGB16161616 4% 2% 0% 2% 0%
AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 64B) XRGB16161616 4% 2% 0% 2% 0%
AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 64B) XRGB16161616 4% 2% 0% 2% 0%
AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 64B) XRGB16161616 4% 2% 0% 2% 0%
AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 128B) XRGB16161616 4% 2% 0% 2% 0%
AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 128B) XRGB16161616 4% 2% 0% 2% 0%
AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 128B) XRGB16161616 4% 2% 0% 2% 0%
AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 128B) XRGB16161616 4% 2% 0% 2% 0%
AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 256B) XRGB16161616 4% 2% 0% 2% 0%
AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 256B) XRGB16161616 4% 2% 0% 2% 0%
AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 256B) XRGB16161616 4% 2% 0% 2% 0%
AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 256B) XRGB16161616 4% 2% 0% 2% 0%
AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 2, BANK_XOR_BITS = 0) XRGB16161616 19% 13% 0% 13% 0%
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 2, PACKERS = 0) XRGB16161616 8% 4% 0% 4% 0%
AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_D_X, PIPE_XOR_BITS = 2, BANK_XOR_BITS = 0) XRGB16161616 19% 13% 0% 13% 0%
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2, PACKERS = 0) XRGB16161616 8% 4% 0% 4% 0%
AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 3) XRGB16161616 4% 2% 0% 2% 0%
AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 3) XRGB16161616 4% 2% 0% 2% 0%
AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 4) XRGB16161616 4% 2% 0% 2% 0%
AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4) XRGB16161616 4% 2% 0% 2% 0%
AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_D_X, PIPE_XOR_BITS = 4, BANK_XOR_BITS = 4) XRGB16161616 0% 2% 0% 2% 0%
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 2, PACKERS = 1) XRGB16161616 4% 4% 0% 4% 0%
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2, PACKERS = 1) XRGB16161616 4% 4% 0% 4% 0%
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2) XRGB16161616 8% 4% 0% 4% 0%
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) XRGB16161616 8% 4% 0% 4% 0%
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 2, PACKERS = 2) XRGB16161616 8% 4% 0% 4% 0%
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2, PACKERS = 2) XRGB16161616 8% 4% 0% 4% 0%
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2) XRGB16161616 12% 6% 0% 7% 0%
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) XRGB16161616 12% 6% 0% 7% 0%
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 3, PACKERS = 3) XRGB16161616 8% 4% 0% 4% 0%
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 3, PACKERS = 3) XRGB16161616 8% 4% 0% 4% 0%
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 3) XRGB16161616 4% 2% 0% 2% 0%
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) XRGB16161616 4% 2% 0% 2% 0%
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 4, PACKERS = 3) XRGB16161616 4% 2% 0% 2% 0%
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4, PACKERS = 3) XRGB16161616 4% 2% 0% 2% 0%
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 4, PACKERS = 4) XRGB16161616 4% 6% 0% 7% 0%
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4, PACKERS = 4) XRGB16161616 4% 6% 0% 7% 0%
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4) XRGB16161616 4% 2% 0% 2% 0%
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) XRGB16161616 4% 2% 0% 2% 0%
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 5) XRGB16161616 4% 2% 0% 2% 0%
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) XRGB16161616 4% 2% 0% 2% 0%