DRM database formats

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Filters: ARGB16161616 ×

Input formats

The percentages indicate the number of devices supporting the format and modifier. For instance, "50%" in the column for the "i915" driver would mean that half the known Intel devices support that format and modifier.

Modifier	Format	Planes			Drivers
		overlay	primary	cursor	amdgpu	vkms
LINEAR	ARGB16161616	100%	100%	100%	100%	100%
AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_S)	ARGB16161616	68%	50%	0%	51%	0%
AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_D)	ARGB16161616	68%	53%	0%	54%	0%
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_D)	ARGB16161616	26%	14%	0%	14%	0%
AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 2, BANK_XOR_BITS = 0)	ARGB16161616	21%	14%	0%	14%	0%
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 2, PACKERS = 0)	ARGB16161616	5%	3%	0%	3%	0%
AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_D_X, PIPE_XOR_BITS = 2, BANK_XOR_BITS = 0)	ARGB16161616	21%	14%	0%	14%	0%
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2, PACKERS = 0)	ARGB16161616	5%	3%	0%	3%	0%
AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 3)	ARGB16161616	5%	3%	0%	3%	0%
AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 3)	ARGB16161616	5%	3%	0%	3%	0%
AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 4)	ARGB16161616	5%	3%	0%	3%	0%
AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4)	ARGB16161616	5%	3%	0%	3%	0%
AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_D_X, PIPE_XOR_BITS = 4, BANK_XOR_BITS = 4)	ARGB16161616	0%	3%	0%	3%	0%
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 2, PACKERS = 1)	ARGB16161616	5%	6%	0%	6%	0%
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2, PACKERS = 1)	ARGB16161616	5%	6%	0%	6%	0%
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 2, PACKERS = 2)	ARGB16161616	5%	6%	0%	6%	0%
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2, PACKERS = 2)	ARGB16161616	5%	6%	0%	6%	0%
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2)	ARGB16161616	11%	6%	0%	6%	0%
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X)	ARGB16161616	11%	6%	0%	6%	0%
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 3, PACKERS = 3)	ARGB16161616	11%	6%	0%	6%	0%
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 3, PACKERS = 3)	ARGB16161616	11%	6%	0%	6%	0%
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 3)	ARGB16161616	5%	3%	0%	3%	0%
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X)	ARGB16161616	5%	3%	0%	3%	0%
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 4, PACKERS = 3)	ARGB16161616	5%	3%	0%	3%	0%
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4, PACKERS = 3)	ARGB16161616	5%	3%	0%	3%	0%
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 4, PACKERS = 4)	ARGB16161616	5%	8%	0%	9%	0%
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4, PACKERS = 4)	ARGB16161616	5%	8%	0%	9%	0%
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4)	ARGB16161616	5%	3%	0%	3%	0%
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X)	ARGB16161616	5%	3%	0%	3%	0%
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 5)	ARGB16161616	5%	3%	0%	3%	0%
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X)	ARGB16161616	5%	3%	0%	3%	0%