DRM database formats

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Filters: P010 ×

Input formats

The percentages indicate the number of devices supporting the format and modifier. For instance, "50%" in the column for the "i915" driver would mean that half the known Intel devices support that format and modifier.

Modifier	Format	Planes		Drivers
		overlay	primary	amdgpu	i915	msm	nvidia-drm	starfive
LINEAR	P010	100%	100%	100%	100%	100%	100%	100%
I915_X_TILED	P010	33%	31%	0%	100%	0%	0%	0%
I915_Y_TILED	P010	27%	26%	0%	82%	0%	0%	0%
I915_Yf_TILED	P010	12%	11%	0%	35%	0%	0%	0%
I915_Y_TILED_GEN12_MC_CCS	P010	12%	11%	0%	35%	0%	0%	0%
I915_4_TILED	P010	6%	6%	0%	18%	0%	0%	0%
I915_4_TILED_DG2_MC_CCS	P010	6%	6%	0%	18%	0%	0%	0%
AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_S)	P010	27%	30%	80%	0%	0%	0%	0%
AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 2, BANK_XOR_BITS = 0)	P010	8%	9%	25%	0%	0%	0%	0%
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 2, PACKERS = 0)	P010	2%	2%	5%	0%	0%	0%	0%
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2, PACKERS = 0)	P010	2%	2%	5%	0%	0%	0%	0%
AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 3)	P010	2%	2%	5%	0%	0%	0%	0%
AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 3)	P010	2%	2%	5%	0%	0%	0%	0%
AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 4)	P010	2%	2%	5%	0%	0%	0%	0%
AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4)	P010	2%	2%	5%	0%	0%	0%	0%
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 2, PACKERS = 1)	P010	2%	2%	5%	0%	0%	0%	0%
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2, PACKERS = 1)	P010	2%	2%	5%	0%	0%	0%	0%
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 2, PACKERS = 2)	P010	4%	4%	10%	0%	0%	0%	0%
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2, PACKERS = 2)	P010	4%	4%	10%	0%	0%	0%	0%
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2)	P010	2%	2%	5%	0%	0%	0%	0%
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X)	P010	2%	2%	5%	0%	0%	0%	0%
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 3, PACKERS = 3)	P010	2%	4%	10%	0%	0%	0%	0%
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 3, PACKERS = 3)	P010	2%	4%	10%	0%	0%	0%	0%
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 3)	P010	2%	2%	5%	0%	0%	0%	0%
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X)	P010	2%	2%	5%	0%	0%	0%	0%
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 4, PACKERS = 3)	P010	2%	2%	5%	0%	0%	0%	0%
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4, PACKERS = 3)	P010	2%	2%	5%	0%	0%	0%	0%
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 4, PACKERS = 4)	P010	4%	4%	10%	0%	0%	0%	0%
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4, PACKERS = 4)	P010	4%	4%	10%	0%	0%	0%	0%
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4)	P010	2%	2%	5%	0%	0%	0%	0%
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X)	P010	2%	2%	5%	0%	0%	0%	0%
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 5)	P010	2%	2%	5%	0%	0%	0%	0%
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X)	P010	2%	2%	5%	0%	0%	0%	0%
NVIDIA_BLOCK_LINEAR_2D(h=0, k=6, g=2, s=1, c=0)	P010	29%	28%	0%	0%	0%	100%	0%
NVIDIA_BLOCK_LINEAR_2D(h=1, k=6, g=2, s=1, c=0)	P010	29%	28%	0%	0%	0%	100%	0%
NVIDIA_BLOCK_LINEAR_2D(h=2, k=6, g=2, s=1, c=0)	P010	29%	28%	0%	0%	0%	100%	0%
NVIDIA_BLOCK_LINEAR_2D(h=3, k=6, g=2, s=1, c=0)	P010	29%	28%	0%	0%	0%	100%	0%
NVIDIA_BLOCK_LINEAR_2D(h=4, k=6, g=2, s=1, c=0)	P010	29%	28%	0%	0%	0%	100%	0%
NVIDIA_BLOCK_LINEAR_2D(h=5, k=6, g=2, s=1, c=0)	P010	29%	28%	0%	0%	0%	100%	0%
QCOM_COMPRESSED	P010	2%	2%	0%	0%	100%	0%	0%
unknown	P010	2%	2%	0%	0%	0%	0%	100%
unknown	P010	2%	2%	0%	0%	0%	0%	100%
unknown	P010	2%	2%	0%	0%	0%	0%	100%
unknown	P010	2%	2%	0%	0%	0%	0%	100%
unknown	P010	2%	2%	0%	0%	0%	0%	100%
unknown	P010	2%	2%	0%	0%	0%	0%	100%
unknown	P010	2%	2%	0%	0%	0%	0%	100%