DRM database formats

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Filters: ABGR16161616 ×

Input formats

The percentages indicate the number of devices supporting the format and modifier. For instance, "50%" in the column for the "i915" driver would mean that half the known Intel devices support that format and modifier.

Modifier Format Planes Drivers
overlay primary amdgpu nvidia-drm
LINEAR ABGR16161616 100% 100% 100% 100%
AMD(TILE_VERSION = unknown, TILE = unknown) ABGR16161616 4% 2% 2% 0%
AMD(TILE_VERSION = unknown, TILE = unknown) ABGR16161616 4% 2% 2% 0%
AMD(TILE_VERSION = unknown, TILE = unknown) ABGR16161616 4% 2% 2% 0%
AMD(TILE_VERSION = unknown, TILE = unknown) ABGR16161616 4% 2% 2% 0%
AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_S) ABGR16161616 67% 49% 50% 0%
AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_D) ABGR16161616 67% 51% 52% 0%
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_D) ABGR16161616 25% 15% 15% 0%
AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 64B) ABGR16161616 4% 2% 2% 0%
AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 64B) ABGR16161616 4% 2% 2% 0%
AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 64B) ABGR16161616 4% 2% 2% 0%
AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 64B) ABGR16161616 4% 2% 2% 0%
AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 128B) ABGR16161616 4% 2% 2% 0%
AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 128B) ABGR16161616 4% 2% 2% 0%
AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 128B) ABGR16161616 4% 2% 2% 0%
AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 128B) ABGR16161616 4% 2% 2% 0%
AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 256B) ABGR16161616 4% 2% 2% 0%
AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 256B) ABGR16161616 4% 2% 2% 0%
AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 256B) ABGR16161616 4% 2% 2% 0%
AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 256B) ABGR16161616 4% 2% 2% 0%
AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 2, BANK_XOR_BITS = 0) ABGR16161616 21% 15% 15% 0%
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 2, PACKERS = 0) ABGR16161616 8% 5% 5% 0%
AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_D_X, PIPE_XOR_BITS = 2, BANK_XOR_BITS = 0) ABGR16161616 21% 15% 15% 0%
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2, PACKERS = 0) ABGR16161616 8% 5% 5% 0%
AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 3) ABGR16161616 4% 2% 2% 0%
AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 3) ABGR16161616 4% 2% 2% 0%
AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 4) ABGR16161616 4% 2% 2% 0%
AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4) ABGR16161616 4% 2% 2% 0%
AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_D_X, PIPE_XOR_BITS = 4, BANK_XOR_BITS = 4) ABGR16161616 0% 2% 2% 0%
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 2, PACKERS = 1) ABGR16161616 4% 5% 5% 0%
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2, PACKERS = 1) ABGR16161616 4% 5% 5% 0%
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 2, PACKERS = 2) ABGR16161616 8% 5% 5% 0%
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2, PACKERS = 2) ABGR16161616 8% 5% 5% 0%
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2) ABGR16161616 12% 7% 8% 0%
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) ABGR16161616 12% 7% 8% 0%
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 3, PACKERS = 3) ABGR16161616 8% 5% 5% 0%
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 3, PACKERS = 3) ABGR16161616 8% 5% 5% 0%
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 3) ABGR16161616 4% 2% 2% 0%
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) ABGR16161616 4% 2% 2% 0%
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 4, PACKERS = 3) ABGR16161616 4% 2% 2% 0%
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4, PACKERS = 3) ABGR16161616 4% 2% 2% 0%
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 4, PACKERS = 4) ABGR16161616 4% 7% 8% 0%
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4, PACKERS = 4) ABGR16161616 4% 7% 8% 0%
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4) ABGR16161616 4% 2% 2% 0%
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) ABGR16161616 4% 2% 2% 0%
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 5) ABGR16161616 4% 2% 2% 0%
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) ABGR16161616 4% 2% 2% 0%
NVIDIA_BLOCK_LINEAR_2D(h=0, k=6, g=2, s=1, c=0) ABGR16161616 4% 2% 0% 100%
NVIDIA_BLOCK_LINEAR_2D(h=1, k=6, g=2, s=1, c=0) ABGR16161616 4% 2% 0% 100%
NVIDIA_BLOCK_LINEAR_2D(h=2, k=6, g=2, s=1, c=0) ABGR16161616 4% 2% 0% 100%
NVIDIA_BLOCK_LINEAR_2D(h=3, k=6, g=2, s=1, c=0) ABGR16161616 4% 2% 0% 100%
NVIDIA_BLOCK_LINEAR_2D(h=4, k=6, g=2, s=1, c=0) ABGR16161616 4% 2% 0% 100%
NVIDIA_BLOCK_LINEAR_2D(h=5, k=6, g=2, s=1, c=0) ABGR16161616 4% 2% 0% 100%