LINEAR |
ABGR16161616 |
100% |
100% |
100% |
AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_S) |
ABGR16161616 |
75% |
53% |
53% |
AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_D) |
ABGR16161616 |
75% |
56% |
56% |
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_D) |
ABGR16161616 |
25% |
14% |
14% |
AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 2, BANK_XOR_BITS = 0) |
ABGR16161616 |
25% |
17% |
17% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 2, PACKERS = 0) |
ABGR16161616 |
5% |
3% |
3% |
AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_D_X, PIPE_XOR_BITS = 2, BANK_XOR_BITS = 0) |
ABGR16161616 |
25% |
17% |
17% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2, PACKERS = 0) |
ABGR16161616 |
5% |
3% |
3% |
AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 3) |
ABGR16161616 |
5% |
3% |
3% |
AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 3) |
ABGR16161616 |
5% |
3% |
3% |
AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 4) |
ABGR16161616 |
5% |
3% |
3% |
AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4) |
ABGR16161616 |
5% |
3% |
3% |
AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_D_X, PIPE_XOR_BITS = 4, BANK_XOR_BITS = 4) |
ABGR16161616 |
0% |
3% |
3% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 2, PACKERS = 1) |
ABGR16161616 |
5% |
6% |
6% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2, PACKERS = 1) |
ABGR16161616 |
5% |
6% |
6% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 2, PACKERS = 2) |
ABGR16161616 |
10% |
6% |
6% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2, PACKERS = 2) |
ABGR16161616 |
10% |
6% |
6% |
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2) |
ABGR16161616 |
10% |
6% |
6% |
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) |
ABGR16161616 |
10% |
6% |
6% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 3, PACKERS = 3) |
ABGR16161616 |
10% |
6% |
6% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 3, PACKERS = 3) |
ABGR16161616 |
10% |
6% |
6% |
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 3) |
ABGR16161616 |
5% |
3% |
3% |
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) |
ABGR16161616 |
5% |
3% |
3% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 4, PACKERS = 3) |
ABGR16161616 |
5% |
3% |
3% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4, PACKERS = 3) |
ABGR16161616 |
5% |
3% |
3% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 4, PACKERS = 4) |
ABGR16161616 |
5% |
8% |
8% |
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4, PACKERS = 4) |
ABGR16161616 |
5% |
8% |
8% |
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4) |
ABGR16161616 |
5% |
3% |
3% |
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) |
ABGR16161616 |
5% |
3% |
3% |
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 5) |
ABGR16161616 |
5% |
3% |
3% |
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) |
ABGR16161616 |
5% |
3% |
3% |