DRM database formats

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Filters: ABGR16161616 ×

Input formats

The percentages indicate the number of devices supporting the format and modifier. For instance, "50%" in the column for the "i915" driver would mean that half the known Intel devices support that format and modifier.

Modifier	Format	Planes		Drivers
		overlay	primary	amdgpu
LINEAR	ABGR16161616	100%	100%	100%
AMD(TILE_VERSION = unknown, TILE = unknown)	ABGR16161616	5%	3%	3%
AMD(TILE_VERSION = unknown, TILE = unknown)	ABGR16161616	5%	3%	3%
AMD(TILE_VERSION = unknown, TILE = unknown)	ABGR16161616	5%	3%	3%
AMD(TILE_VERSION = unknown, TILE = unknown)	ABGR16161616	5%	3%	3%
AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_S)	ABGR16161616	68%	50%	50%
AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_D)	ABGR16161616	68%	53%	53%
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_D)	ABGR16161616	27%	16%	16%
AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 64B)	ABGR16161616	5%	3%	3%
AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 64B)	ABGR16161616	5%	3%	3%
AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 64B)	ABGR16161616	5%	3%	3%
AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 64B)	ABGR16161616	5%	3%	3%
AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 128B)	ABGR16161616	5%	3%	3%
AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 128B)	ABGR16161616	5%	3%	3%
AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 128B)	ABGR16161616	5%	3%	3%
AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 128B)	ABGR16161616	5%	3%	3%
AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 256B)	ABGR16161616	5%	3%	3%
AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 256B)	ABGR16161616	5%	3%	3%
AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 256B)	ABGR16161616	5%	3%	3%
AMD(TILE_VERSION = unknown, TILE = unknown, DCC, DCC_MAX_COMPRESSED_BLOCK = 256B)	ABGR16161616	5%	3%	3%
AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 2, BANK_XOR_BITS = 0)	ABGR16161616	23%	16%	16%
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 2, PACKERS = 0)	ABGR16161616	5%	3%	3%
AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_D_X, PIPE_XOR_BITS = 2, BANK_XOR_BITS = 0)	ABGR16161616	23%	16%	16%
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2, PACKERS = 0)	ABGR16161616	5%	3%	3%
AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 3)	ABGR16161616	5%	3%	3%
AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 3)	ABGR16161616	5%	3%	3%
AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 4)	ABGR16161616	5%	3%	3%
AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4)	ABGR16161616	5%	3%	3%
AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_D_X, PIPE_XOR_BITS = 4, BANK_XOR_BITS = 4)	ABGR16161616	0%	3%	3%
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 2, PACKERS = 1)	ABGR16161616	5%	5%	5%
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2, PACKERS = 1)	ABGR16161616	5%	5%	5%
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 2, PACKERS = 2)	ABGR16161616	9%	5%	5%
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2, PACKERS = 2)	ABGR16161616	9%	5%	5%
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2)	ABGR16161616	14%	8%	8%
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X)	ABGR16161616	14%	8%	8%
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 3, PACKERS = 3)	ABGR16161616	9%	5%	5%
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 3, PACKERS = 3)	ABGR16161616	9%	5%	5%
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 3)	ABGR16161616	5%	3%	3%
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X)	ABGR16161616	5%	3%	3%
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 4, PACKERS = 3)	ABGR16161616	5%	3%	3%
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4, PACKERS = 3)	ABGR16161616	5%	3%	3%
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 4, PACKERS = 4)	ABGR16161616	5%	8%	8%
AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4, PACKERS = 4)	ABGR16161616	5%	8%	8%
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4)	ABGR16161616	5%	3%	3%
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X)	ABGR16161616	5%	3%	3%
AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 5)	ABGR16161616	5%	3%	3%
AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X)	ABGR16161616	5%	3%	3%