LINEAR |
ABGR16161616 |
100% |
100% |
100% |

AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_S) |
ABGR16161616 |
81% |
53% |
53% |

AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_D) |
ABGR16161616 |
81% |
56% |
56% |

AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_D) |
ABGR16161616 |
19% |
12% |
12% |

AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 2, BANK_XOR_BITS = 0) |
ABGR16161616 |
25% |
15% |
15% |

AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 2, PACKERS = 0) |
ABGR16161616 |
6% |
3% |
3% |

AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_D_X, PIPE_XOR_BITS = 2, BANK_XOR_BITS = 0) |
ABGR16161616 |
25% |
15% |
15% |

AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2, PACKERS = 0) |
ABGR16161616 |
6% |
3% |
3% |

AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 3) |
ABGR16161616 |
6% |
3% |
3% |

AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 3) |
ABGR16161616 |
6% |
3% |
3% |

AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 4) |
ABGR16161616 |
6% |
3% |
3% |

AMD(TILE_VERSION = GFX10, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4) |
ABGR16161616 |
6% |
3% |
3% |

AMD(TILE_VERSION = GFX9, TILE = GFX9_64K_D_X, PIPE_XOR_BITS = 4, BANK_XOR_BITS = 4) |
ABGR16161616 |
0% |
3% |
3% |

AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 2, PACKERS = 1) |
ABGR16161616 |
6% |
6% |
6% |

AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2, PACKERS = 1) |
ABGR16161616 |
6% |
6% |
6% |

AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 2, PACKERS = 2) |
ABGR16161616 |
6% |
6% |
6% |

AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2, PACKERS = 2) |
ABGR16161616 |
6% |
6% |
6% |

AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 2) |
ABGR16161616 |
6% |
3% |
3% |

AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) |
ABGR16161616 |
6% |
3% |
3% |

AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 3, PACKERS = 3) |
ABGR16161616 |
12% |
6% |
6% |

AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 3, PACKERS = 3) |
ABGR16161616 |
12% |
6% |
6% |

AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 3) |
ABGR16161616 |
0% |
3% |
3% |

AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) |
ABGR16161616 |
0% |
3% |
3% |

AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 4, PACKERS = 3) |
ABGR16161616 |
6% |
3% |
3% |

AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4, PACKERS = 3) |
ABGR16161616 |
6% |
3% |
3% |

AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_S_X, PIPE_XOR_BITS = 4, PACKERS = 4) |
ABGR16161616 |
6% |
9% |
9% |

AMD(TILE_VERSION = GFX10_RBPLUS, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4, PACKERS = 4) |
ABGR16161616 |
6% |
9% |
9% |

AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 4) |
ABGR16161616 |
6% |
3% |
3% |

AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) |
ABGR16161616 |
6% |
3% |
3% |

AMD(TILE_VERSION = GFX11, TILE = GFX9_64K_R_X, PIPE_XOR_BITS = 5) |
ABGR16161616 |
6% |
3% |
3% |

AMD(TILE_VERSION = GFX11, TILE = GFX11_256K_R_X) |
ABGR16161616 |
6% |
3% |
3% |